公开(公告)号：US20180018118A1

公开(公告)日：2018-01-18

申请号：US15211607

申请日：2016-07-15

Applicant: QUALCOMM Incorporated

Inventor： Sharath Raghava ,  Jhy-ping Shaw ,  Vinodh Cuppu ,  Paul Min

IPC: G06F3/06 ,  G06F1/32 ,  G06F1/12

CPC classification number: G06F1/12 ,  G06F1/08 ,  G06F1/10 ,  G06F1/324 ,  G06F1/3275 ,  G06F12/10 ,  G06F2212/1028 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: In one embodiment, a method for power management includes receiving one or more state signals, each of the one or more state signals indicating whether a respective sub-block of a memory controller is idle or active, and determining whether to place the memory controller in an idle state or an active state based on the one or more state signals. The method also includes eating pulses of an input clock signal to produce a reduced-frequency clock signal if a determination is made to place the memory controller in the idle state, wherein the reduced-frequency clock signal is output to the memory controller. The method further includes passing the input clock signal to the memory controller if a determination is made to place the memory controller in the active state.

公开(公告)号：US09246716B2

公开(公告)日：2016-01-26

申请号：US14663303

申请日：2015-03-19

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Sumeet Sethi ,  John Eaton ,  Vinodh Cuppu ,  Vikram Arora ,  Vaishnav Srinivas ,  Asim Muhammad Muneer ,  Isaac Berk

IPC: H03K19/003 ,  H04L25/02 ,  H03K19/0175 ,  G06F13/40 ,  H03K19/00

CPC classification number: H04L25/0278 ,  G06F13/4086 ,  H03K19/0005 ,  H03K19/017545 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus.