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公开(公告)号：US10236266B2
公开(公告)日：2019-03-19
申请号：US15594696
申请日：2017-05-15
Inventor： Atsushi Harikai , Shogo Okita , Akihiro Itou , Katsumi Takano , Mitsuru Hiroshima
IPC: H01L21/48 , H01L21/67 , H01L21/687 , H01L23/498 , H05K13/04 , H01L23/00 , B44C1/22
Abstract: An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface having an exposed bump and a second surface opposite to the first surface and includes a plurality of element regions defined by dividing regions, a bump embedding process of embedding at least a head top part of the bump into the adhesive layer, a mask forming process of forming a mask in the second surface. The method for manufacturing the element chip includes a holding process of arranging the first surface to oppose a holding tape supported on a frame and holding the substrate on the holding tape, a placement process of placing the substrate on a stage provided inside of a plasma processing apparatus through the holding tape, after the mask forming process and the holding process.
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公开(公告)号：US10026619B2
公开(公告)日：2018-07-17
申请号：US15426192
申请日：2017-02-07
Inventor： Shogo Okita , Atsushi Harikai
IPC: B44C1/22 , H01L21/3065 , H01L21/308 , H01L21/677
Abstract: The yield of a product is improved when a substrate held by a conveyance carrier is subjected to a plasma treatment. A plasma treatment method of the substrate held by the conveyance carrier includes preparing the conveyance carrier which includes a holding sheet and a frame disposed on the outer peripheral portion of the holding sheet; bonding the substrate to the holding sheet so that the substrate is held by the conveyance carrier; and increasing tensile strength of the holding sheet. The plasma treatment method further includes placing the conveyance carrier on the stage after the bonding of the substrate and bringing the substrate into contact with the stage through the holding sheet; and performing a plasma treatment on the substrate after the placing of the conveyance carrier.
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公开(公告)号：US09941132B2
公开(公告)日：2018-04-10
申请号：US15000789
申请日：2016-01-19
Inventor： Shogo Okita , Atsushi Harikai , Noriyuki Matsubara
IPC: H01L21/302 , H01L21/3065 , H01L21/78 , H01J37/32 , H01L21/67 , H01L21/683 , H01L21/687
CPC classification number: H01L21/3065 , H01J37/32568 , H01J37/32697 , H01J37/32715 , H01J37/32724 , H01L21/67109 , H01L21/6833 , H01L21/6836 , H01L21/68742 , H01L21/78 , H01L2221/68327
Abstract: A plasma processing apparatus includes: a reaction chamber; a plasma generation unit; a stage disposed inside the reaction chamber; an electrostatic chuck mechanism including an electrode portion inside the stage; a heater inside the stage; a support portion which supports a conveyance carrier between a stage-mounted position on the stage and a transfer position distant from the stage upward; and an elevation mechanism which elevates and lowers the support portion relative to the stage. In a case in which the conveyance carrier is mounted on the stage by lowering the support portion, application of voltage to the electrode portion is started in a state that the stage is being heated, and the plasma generation unit generates plasma after at least a part of an outer circumferential portion of a holding sheet holding the conveyance carrier contacts the stage and also after the heating of the stage is stopped.
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公开(公告)号：US09911677B2
公开(公告)日：2018-03-06
申请号：US15427548
申请日：2017-02-08
Inventor： Bunzi Mizuno , Mitsuru Hiroshima , Shogo Okita , Noriyuki Matsubara , Atsushi Harikai
IPC: H01L23/31 , H01L21/311 , H01L21/428 , H01L21/56 , H01L21/78 , H01L23/544
CPC classification number: H01L23/3192 , H01L21/0212 , H01L21/02274 , H01L21/3065 , H01L21/30655 , H01L21/3086 , H01L21/31116 , H01L21/31138 , H01L21/428 , H01L21/561 , H01L21/6836 , H01L21/78 , H01L23/3185 , H01L23/544 , H01L2221/68327 , H01L2221/68381 , H01L2223/5446
Abstract: A method for manufacturing an element chip includes a protection film etching step of removing a part of the protection film which is stacked on the dividing region and the protection film which is stacked on the element region through etching the protection film anisotropically by exposing the substrate to first plasma and remaining the protection film for covering an end surface of the element region. Furthermore, the method for manufacturing an element chip includes an isotropic etching step of etching the dividing region isotropically by exposing the substrate to second plasma and a plasma dicing step of dividing the substrate to a plurality of element chips including the element region by exposing the substrate to third plasma in a state where the second main surface is supported by a supporting member.
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公开(公告)号：US09698052B2
公开(公告)日：2017-07-04
申请号：US15267059
申请日：2016-09-15
Inventor： Atsushi Harikai , Shogo Okita , Noriyuki Matsubara
IPC: H01L21/78 , H01L21/02 , H01L21/3065 , H01L21/48 , H01L21/683 , H01L23/29 , H01L23/00 , H01L21/60
CPC classification number: H01L21/78 , H01L21/0212 , H01L21/02274 , H01L21/3065 , H01L21/30655 , H01L21/31138 , H01L21/4853 , H01L21/6835 , H01L23/293 , H01L24/32 , H01L24/83 , H01L2021/60007 , H01L2221/68327 , H01L2221/6834 , H01L2224/03849 , H01L2224/26145 , H01L2224/32168 , H01L2224/83815
Abstract: In a method of manufacturing an element chip for manufacturing a plurality of element chips by dividing a substrate, where the protruding portions, which are exposed element electrodes, are formed on element regions, protection films made of fluorocarbon film are formed on a second surface and side surfaces of the element chip, and a first surface in a gap by exposing the element chip to second plasma after the substrate is divided by etching. Next, the protection films formed on the second surface and the side surfaces of the element chip are removed while leaving at least a part of the protection film formed in the gap by exposing the element chip to third plasma. Therefore, creep-up of a conductive material in a mounting step is suppressed by the left protection film.
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Patent Agency Ranking
公开(公告)号：US09570272B2
公开(公告)日：2017-02-14
申请号：US15000374
申请日：2016-01-19
Inventor： Shogo Okita , Atsushi Harikai , Noriyuki Matsubara
IPC: H01J37/32 , H01L21/683 , H01L21/687
CPC classification number: H01J37/32009 , H01J37/321 , H01J37/3244 , H01J37/32715 , H01J37/32733 , H01J2237/334 , H01L21/6833 , H01L21/68742
Abstract: A plasma processing apparatus includes: a reaction chamber; a stage which is disposed inside the reaction chamber and on which a conveyance carrier is mountable; an electrostatic chuck mechanism including an electrode portion that is disposed inside the stage; a support portion which supports the conveyance carrier between a stage-mounted position on the stage and a transfer position that is distant from the stage upward; and an elevation mechanism which elevates and lowers the support portion relative to the stage. In a case in which the conveyance carrier is mounted on the stage by lowering the support portion, the electrostatic chuck mechanism starts applying a voltage to the electrode portion before contact of an outer circumferential portion of a holding sheet which holds the conveyance carrier to the stage.
Abstract translation: 一种等离子体处理装置，包括：反应室; 设置在反应室内的台架，输送载体可安装在该台上; 静电吸盘机构，其包括设置在所述台内部的电极部; 支撑部分，其在台架上的台安装位置和远离台架的传送位置之间支撑传送载体; 以及升降机构，其使支撑部相对于台升高并降低。 在通过降低支撑部分而将输送载体安装在载物台上的情况下，静电卡盘机构在将保持输送载体的保持片材的外周部分接触到台架之前开始向电极部分施加电压 。
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公开(公告)号：US12230541B2
公开(公告)日：2025-02-18
申请号：US17456914
申请日：2021-11-30
Inventor： Atsushi Harikai , Shogo Okita , Akihiro Itou , Toshiyuki Takasaki
IPC: H01L21/78 , H01L21/304 , H01L21/3065
Abstract: The element chip manufacturing method includes: a preparing process of preparing a substrate 1 including a plurality of element regions EA and a dividing region DA, the substrate 1 having a first principal surface 1X and a second principal surface 1Y; a groove forming process of forming a groove 13 in the dividing region DA from the first principal surface 1X side; and a grinding process of grinding the substrate 1 from the second principal surface 1Y side, to divide the substrate 1 into a plurality of element chips 20. The groove 13 includes a first region 13a constituted by a side surface having a first surface roughness, and a second region 13b constituted by a side surface having a second surface roughness larger than the first surface roughness. In the grinding process, grinding of the substrate 1 is performed until reaching the first region 13a of the groove 13.
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公开(公告)号：US12230484B2
公开(公告)日：2025-02-18
申请号：US17937512
申请日：2022-10-03
Inventor： Atsushi Harikai , Shogo Okita
IPC: H01J37/32
Abstract: A plasma processing apparatus including: a chamber; a plasma generation unit configured to generate a plasma in the chamber; a stage 111 for placing a conveying carrier 10, the stage provided in the chamber; a cover 124 for covering at least part of the conveying carrier placed on the stage; a relative position change unit capable of changing a relative distance between the cover 124 and the stage 111 to a first distance and to a second distance smaller than the first distance; a determination unit configured to determine a placed state of the conveying carrier 10; and a control unit. The determination unit determines the placed state of the conveying carrier while the distance between the cover 124 and the stage 111 is the first distance, and the plasma processing is performed while the distance between the cover 124 and the stage 111 is the second distance.
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公开(公告)号：US11688641B2
公开(公告)日：2023-06-27
申请号：US16881165
申请日：2020-05-22
Inventor： Hidefumi Saeki , Hidehiko Karasaki , Shogo Okita , Atsushi Harikai , Akihiro Itou
IPC: H01L21/82 , H01L21/56 , H01L21/3065 , H01L21/311 , H01L21/78
CPC classification number: H01L21/82 , H01L21/3065 , H01L21/31122 , H01L21/31127 , H01L21/568
Abstract: An element chip manufacturing method including: attaching a substrate via a die attach film (DAF) to a holding sheet; forming a protective film that covers the substrate; forming an opening in the protective film with a laser beam, to expose the substrate in the dicing region therefrom; exposing the substrate to a first plasma to etch the substrate exposed from the opening, so that a plurality of element chips are formed from the substrate and so that the DAF is exposed from the opening; exposing the substrate to a second plasma to etch the die attach film exposed from the opening, so that the DAF is split so as to correspond to the element chips; and detaching the element chips from the holding sheet, together with the split DAF. The DAF is larger than the substrate. The method includes irradiating the laser beam to the DAF protruding from the substrate.
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公开(公告)号：US11551974B2
公开(公告)日：2023-01-10
申请号：US17471661
申请日：2021-09-10
Inventor： Hidefumi Saeki , Atsushi Harikai , Shogo Okita
IPC: H01L21/78 , H01L23/544 , H01L21/268 , B23K26/00 , B23K26/364 , H01L21/3065
Abstract: A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.
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