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31.发明申请公开(公告)号：US20170076955A1
公开(公告)日：2017-03-16
申请号：US15364101
申请日：2016-11-29
发明人： Eric A. Hudson , Nikhil Dole
IPC分类号： H01L21/3065 , C23C16/52 , C23C16/455 , C23C16/50 , H01L21/02 , H01J37/32
CPC分类号： H01L21/30655 , C23C16/45544 , C23C16/50 , C23C16/52 , H01J37/32009 , H01J37/3244 , H01J2237/334 , H01L21/02164 , H01L21/02274 , H01L21/0228 , H01L21/02532 , H01L21/0262 , H01L21/31116 , H01L21/31144 , H01L21/67069 , H01L21/67167 , H01L21/67207 , H01L21/67259 , H01L21/67745 , H01L21/68785
摘要： Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in substantial preservation of a mask layer on the substrate. The protective coating may be deposited using particular reactants and/or reaction conditions that are unlikely to damage the mask layer. The protective coating may also be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. In some cases the protective coating is deposited using plasma assisted atomic layer deposition, a modified plasma assisted atomic layer deposition, or plasma assisted chemical vapor deposition.
摘要翻译： 本文中的各种实施例涉及用于在基板上的电介质材料中形成凹陷特征的方法，装置和系统。 以循环方式采用分离的蚀刻和沉积操作。 每个蚀刻操作部分地蚀刻该特征。 每个沉积操作在特征的侧壁上形成保护涂层，以防止在蚀刻操作期间电介质材料的横向蚀刻。 可以使用导致基材上的掩模层的实质性保存的方法来沉积保护涂层。 可以使用不太可能损害掩模层的特定反应物和/或反应条件沉积保护涂层。 保护涂层也可以使用特定的反应机理沉积，这导致基本上完全的侧壁涂覆。 在一些情况下，使用等离子体辅助原子层沉积，改进的等离子体辅助原子层沉积或等离子体辅助化学气相沉积来沉积保护涂层。
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32.发明申请公开(公告)号：US20160163557A1
公开(公告)日：2016-06-09
申请号：US14697521
申请日：2015-04-27
发明人： Eric A. Hudson , Nikhil Dole
IPC分类号： H01L21/3065 , H01L21/308 , H01L21/67 , H01L21/02
CPC分类号： H01L21/30655 , H01J37/32091 , H01J37/32165 , H01J37/32513 , H01J37/32568 , H01J37/32715 , H01J37/32908 , H01L21/02112 , H01L21/02164 , H01L21/02167 , H01L21/0217 , H01L21/02271 , H01L21/02274 , H01L21/0228 , H01L21/02532 , H01L21/0262 , H01L21/3081 , H01L21/31116 , H01L21/67069 , H01L21/68785
摘要： Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in substantial preservation of a mask layer on the substrate. The protective coating may be deposited using particular reactants and/or reaction conditions that are unlikely to damage the mask layer. The protective coating may also be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. In some cases the protective coating is deposited using plasma assisted atomic layer deposition, a modified plasma assisted atomic layer deposition, or plasma assisted chemical vapor deposition.
摘要翻译： 本文中的各种实施例涉及用于在基板上的电介质材料中形成凹陷特征的方法，装置和系统。 以循环方式采用分离的蚀刻和沉积操作。 每个蚀刻操作部分地蚀刻该特征。 每个沉积操作在特征的侧壁上形成保护涂层，以防止在蚀刻操作期间电介质材料的横向蚀刻。 可以使用导致基材上的掩模层的实质性保存的方法来沉积保护涂层。 可以使用不太可能损害掩模层的特定反应物和/或反应条件沉积保护涂层。 保护涂层也可以使用特定的反应机理沉积，这导致基本上完全的侧壁涂覆。 在一些情况下，使用等离子体辅助原子层沉积，改进的等离子体辅助原子层沉积或等离子体辅助化学气相沉积来沉积保护涂层。
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33.发明申请公开(公告)号：US20160163556A1
公开(公告)日：2016-06-09
申请号：US14560414
申请日：2014-12-04
IPC分类号： H01L21/3065 , H01L21/02 , C23C16/455 , H01J37/32 , C23C16/52 , C23C16/50
CPC分类号： H01L21/31116 , H01J37/32009 , H01J37/32091 , H01J37/3244 , H01J37/32513 , H01J37/32577 , H01J37/32623 , H01J37/32651 , H01J37/32871 , H01J37/32899 , H01J2237/334 , H01L21/02112 , H01L21/02164 , H01L21/0217 , H01L21/02271 , H01L21/02274 , H01L21/0228 , H01L21/30655 , H01L27/108 , H01L27/115
摘要： Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reactants having low sticking coefficients in some embodiments. The protective coating may also be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. In some cases the protective coating is deposited using plasma assisted atomic layer deposition or plasma assisted chemical vapor deposition.
摘要翻译： 本文的各种实施例涉及用于在半导体衬底上的电介质材料中形成凹陷特征的方法，装置和系统。 以循环方式采用分离的蚀刻和沉积操作。 每个蚀刻操作部分地蚀刻该特征。 每个沉积操作在特征的侧壁上形成保护涂层，以防止在蚀刻操作期间电介质材料的横向蚀刻。 保护涂层可以使用沿着侧壁的大致整个长度形成保护涂层的方法进行沉积。 在一些实施方案中，可以使用具有低粘附系数的特定反应物来沉积保护性涂层。 保护涂层也可以使用特定的反应机理沉积，这导致基本上完全的侧壁涂覆。 在一些情况下，使用等离子体辅助原子层沉积或等离子体辅助化学气相沉积来沉积保护涂层。
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公开(公告)号：US09263331B2
公开(公告)日：2016-02-16
申请号：US14801624
申请日：2015-07-16
发明人： Ananth Indrakanti , Peng Wang , Eric A. Hudson
IPC分类号： H01L21/4763 , H01L21/768 , H01L21/311 , H01L21/3105 , H01L21/67 , H01J37/32
CPC分类号： H01L21/76897 , H01J37/32082 , H01J37/32091 , H01J37/32449 , H01J37/32532 , H01J37/32715 , H01J2237/332 , H01J2237/334 , H01L21/31051 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/67069 , H01L21/6831 , H01L21/76802 , H01L21/76811 , H01L21/76819 , H01L21/76877
摘要： A method of etching self-aligned contact/via features in a low-k dielectric layer disposed below a hardmask, which is disposed below a planarization layer. At least one cycle is provided, where each cycle comprises thinning the planarization layer, forming a deposition layer on the hardmask and planarization layer; and etching the low-k dielectric layer masked by the deposition layer.
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公开(公告)号：US09039911B2
公开(公告)日：2015-05-26
申请号：US13626793
申请日：2012-09-25
IPC分类号： B44C1/22 , H01J37/32 , H01L21/311
CPC分类号： H01L21/3065 , H01J37/32009 , H01J37/32091 , H01J37/321 , H01J37/32192 , H01J37/32357 , H01J37/32449 , H01J37/32458 , H01J37/32715 , H01J2237/334 , H01L21/31116 , H01L21/31138 , H01L21/32136 , H01L21/67069
摘要： Methods for etching a substrate in a plasma processing chamber having at least a primary plasma generating region and a secondary plasma generating region separated from said primary plasma generating region by a semi-barrier structure. The method includes generating a primary plasma from a primary feed gas in the primary plasma generating region. The method also includes generating a secondary plasma from a secondary feed gas in the secondary plasma generating region to enable at least some species from the secondary plasma to migrate into the primary plasma generating region. The method additionally includes etching the substrate with the primary plasma after the primary plasma has been augmented with migrated species from the secondary plasma.
摘要翻译： 用于蚀刻具有至少一个初级等离子体产生区域的等离子体处理室中的衬底和通过半屏障结构从所述初级等离子体产生区域分离的次级等离子体产生区域的方法。 该方法包括从主要等离子体产生区域中的主进料气体产生主要等离子体。 该方法还包括从次级等离子体产生区域中的二次进料气体产生二次等离子体，以使至少一些来自第二等离子体的物质迁移到初级等离子体产生区域。 该方法另外包括在初级等离子体已经用来自二次等离子体的迁移物质增强之后用初级等离子体蚀刻基板。
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公开(公告)号：US08470126B2
公开(公告)日：2013-06-25
申请号：US13629129
申请日：2012-09-27
IPC分类号： C23C16/52 , C23C16/50 , C23C16/503 , C23F1/00 , H01L21/306 , G05B15/00 , G06F17/00 , C23C16/06 , C23C16/22
CPC分类号： H01L21/31116 , H01L21/31144
摘要： An apparatus for etching features in an etch layer is provided. A plasma processing chamber is provided, comprising a chamber wall, a chuck, a pressure regulator, an electrode or coil, a gas inlet, and a gas outlet. A gas source comprises a fluorine free deposition gas source and an etch gas source. A controller comprises at least one processor and computer readable media, comprising computer readable code for providing a conditioning for a patterned pseudo-hardmask, wherein the conditioning comprises computer readable code providing a fluorine free deposition gas comprising a hydrocarbon gas, computer readable code for forming a plasma, computer readable code for providing a bias less than 500 volts, and computer readable code for forming a deposition on top of the patterned pseudo-hardmask, computer readable code for etching the etch layer, and computer readable code for cyclically repeating the conditioning and etching at least twice.
摘要翻译： 提供了用于蚀刻蚀刻层中的特征的设备。 提供了等离子体处理室，其包括室壁，卡盘，压力调节器，电极或线圈，气体入口和气体出口。 气源包括无氟沉积气体源和蚀刻气体源。 控制器包括至少一个处理器和计算机可读介质，其包括用于为图案化伪硬掩模提供调节的计算机可读代码，其中所述调节包括提供包含烃气体的无氟沉积气体的计算机可读代码，用于形成的计算机可读代码 用于提供小于500伏特的偏置的等离子体，计算机可读代码以及用于在图案化伪硬掩模上形成沉积的计算机可读代码，用于蚀刻蚀刻层的计算机可读代码以及用于循环重复调节的计算机可读代码 并蚀刻至少两次。
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公开(公告)号：US20130020026A1
公开(公告)日：2013-01-24
申请号：US13629129
申请日：2012-09-27
IPC分类号： H01L21/3065
CPC分类号： H01L21/31116 , H01L21/31144
摘要： An apparatus for etching features in an etch layer is provided. A plasma processing chamber is provided, comprising a chamber wall, a chuck, a pressure regulator, an electrode or coil, a gas inlet, and a gas outlet. A gas source comprises a fluorine free deposition gas source and an etch gas source. A controller comprises at least one processor and computer readable media, comprising computer readable code for providing a conditioning for a patterned pseudo-hardmask, wherein the conditioning comprises computer readable code providing a fluorine free deposition gas comprising a hydrocarbon gas, computer readable code for forming a plasma, computer readable code for providing a bias less than 500 volts, and computer readable code for forming a deposition on top of the patterned pseudo-hardmask, computer readable code for etching the etch layer, and computer readable code for cyclically repeating the conditioning and etching at least twice.
摘要翻译： 提供了用于蚀刻蚀刻层中的特征的设备。 提供了等离子体处理室，其包括室壁，卡盘，压力调节器，电极或线圈，气体入口和气体出口。 气源包括无氟沉积气体源和蚀刻气体源。 控制器包括至少一个处理器和计算机可读介质，其包括用于为图案化伪硬掩模提供调节的计算机可读代码，其中所述调节包括提供包含烃气体的无氟沉积气体的计算机可读代码，用于形成的计算机可读代码 用于提供小于500伏特的偏置的等离子体，计算机可读代码以及用于在图案化伪硬掩模上形成沉积的计算机可读代码，用于蚀刻蚀刻层的计算机可读代码以及用于循环重复调节的计算机可读代码 并蚀刻至少两次。
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公开(公告)号：US20230127597A1
公开(公告)日：2023-04-27
申请号：US17907401
申请日：2021-03-10
发明人： Rui Takahashi , Yilun Li , Eric A. Hudson , Youn-Jin Oh , Wonjae Lee , Leonid Belau , Andrew Clark Serino
IPC分类号： H01L21/311 , H01L21/3213 , H01J37/32
摘要： Various embodiments herein relate to methods and apparatus for etching recessed features on a semiconductor substrate. The techniques described herein can be used to form high quality recessed features with a substantially vertical profile, low bowing, low twisting, and highly circular features. These high quality results can be achieved with a high degree of selectivity and a relatively high etch rate. In various embodiments, etching involves exposing the substrate to plasma generated from a processing gas that includes a chlorine source, a carbon source, a hydrogen source, and a fluorine source. The chlorine source may have particular properties. In some cases, particular chlorine sources may be used. Etching typically occurs at low temperatures, for example at about 25C or lower.
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公开(公告)号：US20220282366A1
公开(公告)日：2022-09-08
申请号：US17753208
申请日：2020-08-28
发明人： Matthew Scott Weimer , Ragesh Puthenkovilakam , Gordon Alex Macdonald , Shaoqing Zhang , Shih-Ked Lee , Jun Xue , Samantha S.H. Tan , Xizhu Zhao , Mary Anne Manumpil , Eric A. Hudson , Chin-Jui Hsu
摘要： Provided herein are methods and related apparatus for depositing an ashable hard mask (AHM) on a substrate in a low pressure chamber using a dual frequency radio frequency component. Low pressure plasma enhanced chemical vapor deposition may be used to increase the etch selectivity of the AHM, permitting the use of a thinner AHM for semiconductor processing operations.
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公开(公告)号：US10304693B2
公开(公告)日：2019-05-28
申请号：US15846018
申请日：2017-12-18
发明人： Eric A. Hudson
IPC分类号： H01L21/311 , H01J37/32 , C23C16/50 , C23C16/52 , C23C16/455 , H01L21/3065 , C23C16/00 , C23C16/04 , H01L27/108 , H01L21/02
摘要： Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reactants and/or reaction mechanisms that result in substantially complete sidewall coating at relatively low temperatures without the use of plasma. In some cases the protective coating is deposited using molecular layer deposition techniques. In certain implementations the protective coating is fluorinated.
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