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    Low density parity check decoder with miscorrection handling
    32.
    发明授权
    Low density parity check decoder with miscorrection handling 有权
    低密度奇偶校验解码器与错误处理

    公开(公告)号：US08996969B2

    公开(公告)日：2015-03-31

    申请号：US13708941

    申请日：2012-12-08

    Applicant: LSI Corporation

    Inventor： Anatoli A. Bolotov ,  Shaohua Yang ,  Zongwang Li ,  Mikhail I Grinchuk ,  Lav D. Ivanovic ,  Fan Zhang ,  Yang Han

    IPC: H03M13/00 ,  H03M13/13 ,  H03M13/11

    CPC classification number: H03M13/13 ,  H03M13/1111 ,  H03M13/1142

    Abstract: A data processing system includes a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a second portion of the composite matrix. The decoder circuit is also operable to correct the codeword on the hash when the syndrome indicates that the codeword based on the first portion of the composite matrix is correct but a second test indicates that the codeword is miscorrected.

    Abstract translation: 数据处理系统包括解码器电路，校正子计算电路和散列计算电路。 解码器电路可操作以基于复合矩阵的第一部分将解码算法应用于解码器输入以产生码字。 校正子计算电路可操作以基于码字和复合矩阵的第一部分来计算校正子。 散列计算电路可操作以基于复合矩阵的第二部分来计算散列。 当校验子指示基于复合矩阵的第一部分的码字是正确的但是第二测试指示码字被修正时，解码器电路还可操作以校正散列上的码字。

    Shift Register-Based Layered Low Density Parity Check Decoder
    33.
    发明申请
    Shift Register-Based Layered Low Density Parity Check Decoder 有权
    基于移位寄存器的分层低密度奇偶校验解码器

    公开(公告)号：US20140351671A1

    公开(公告)日：2014-11-27

    申请号：US13898685

    申请日：2013-05-21

    Applicant: LSI Corporation

    Inventor： Dan Liu ,  Qi Zuo ,  Chung-Li Wang ,  Zongwang Li ,  Lei Wang

    IPC: H03M13/11

    CPC classification number: H03M13/1105 ,  H03M13/1114 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1122 ,  H03M13/1131 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/116 ,  H03M13/1162 ,  H03M13/1171 ,  H03M13/1174 ,  H03M13/6331 ,  H03M13/6505 ,  H03M13/658 ,  H03M13/6583 ,  H04L1/005

    Abstract: An apparatus for layered low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages. The check node processor includes an intermediate message generator circuit operable to generate intermediate check node messages, a shift register based memory operable to store the intermediate check node messages, and at least one check node to variable node message generator circuit operable to generate the check node to variable node messages based on the intermediate check node messages from the shift register based memory.

    Abstract translation: 用于分层低密度奇偶校验解码的装置包括可变节点处理器和校验节点处理器。 可变节点处理器可操作以生成可变节点以检查节点消息，并且基于校验节点到可变节点消息来计算感知数据值。 校验节点处理器包括可操作以产生中间校验节点消息的中间消息发生器电路，可操作以存储中间校验节点消息的移位寄存器的存储器，以及至少一个校验节点，可变节点消息生成器电路可操作以生成校验节点 基于来自基于移位寄存器的存储器的中间检查节点消息到可变节点消息。

    Low Density Parity Check Decoder With Dynamic Scaling
    37.
    发明申请
    Low Density Parity Check Decoder With Dynamic Scaling 有权
    低密度奇偶校验解码器与动态缩放

    公开(公告)号：US20140173385A1

    公开(公告)日：2014-06-19

    申请号：US13777841

    申请日：2013-02-26

    Applicant: LSI CORPORATION

    Inventor： Shu Li ,  Zongwang Li ,  Shaohua Yang ,  Chung-Li Wang ,  Fan Zhang

    IPC: H03M13/13 ,  G11B20/18

    CPC classification number: H03M13/1117 ,  G11B20/1833 ,  G11B2020/185 ,  H03M13/1111 ,  H03M13/1171 ,  H03M13/27 ,  H03M13/6331 ,  H03M13/658

    Abstract: A data processing system is disclosed including a low density parity check decoder with a variable node processor, a check node processor and a scaler circuit. The low density parity check decoder is operable to scale soft information with a scaling factor in the scaler circuit while iteratively generating and processing check node to variable node messages in the variable node processor and variable node to check node messages in the check node processor between a plurality of check nodes and variable nodes. The scaling factor is derived from a distribution of possible values in an input to the low density parity check decoder.

    Abstract translation: 公开了一种数据处理系统，包括具有可变节点处理器的低密度奇偶校验解码器，校验节点处理器和缩放器电路。 低密度奇偶校验解码器可用于在缩放器电路中缩放具有缩放因子的软信息，同时在可变节点处理器和变量节点中对可变节点消息进行迭代生成并处理校验节点，以校验校验节点处理器中的节点消息 多个检查节点和可变节点。 缩放因子是从低密度奇偶校验解码器的输入中的可能值的分布导出的。

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