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    Method of forming dual gate structure
    31.
    发明授权
    Method of forming dual gate structure 有权
    形成双栅结构的方法

    公开(公告)号：US06214671B1

    公开(公告)日：2001-04-10

    申请号：US09223151

    申请日：1998-12-30

    申请人： Shih-Wei Sun

    发明人： Shih-Wei Sun

    IPC分类号： H01L21336

    CPC分类号： H01L21/823842 ,  H01L21/28052 ,  H01L29/4933 ,  H01L29/665

    摘要： A method of forming a dual gate structure provides a substrate, in which a first well with a first conductive type and a second well with a second conductive type are formed. An isolation structure is formed between the first well and the second well. A gate oxide layer is formed on the substrate. A polysilicon layer is formed on the gate oxide layer. A part of the polysilicon layer positioned on the first well is doped to become a first type polysilicon layer. Another part of the polysilicon layer positioned on the second well is doped to become a second type polysilicon layer. An undoped polysilicon layer is formed on the doped polysilicon layer. A part of the undoped polysilicon and a part of the doped polysilicon layer are removed to form a first gate on the first well and a second gate on the second well. Spacers are formed on the sidewalls of the first gate and on the second gate. Source/drain regions are formed in the substrate beside the first gate and the second gate. Silicide is formed on the first gate, the second gate and the source/drain regions by self-alignment to form a dual gate structure comprising the first gate and the second gate.

    摘要翻译： 形成双栅极结构的方法提供了一种衬底，其中形成具有第一导电类型的第一阱和具有第二导电类型的第二阱。 在第一井和第二井之间形成隔离结构。 在衬底上形成栅氧化层。 在栅氧化层上形成多晶硅层。 位于第一阱的多晶硅层的一部分被掺杂成为第一类型的多晶硅层。 位于第二阱上的多晶硅层的另一部分被掺杂以成为第二类型的多晶硅层。 在掺杂多晶硅层上形成未掺杂的多晶硅层。 去除未掺杂多晶硅的一部分和掺杂多晶硅层的一部分，以在第一阱上形成第一栅极，在第二阱上形成第二栅极。 间隔件形成在第一门的侧壁和第二门上。 源极/漏极区域形成在第一栅极和第二栅极旁边的衬底中。 通过自对准在第一栅极，第二栅极和源极/漏极区域上形成硅化物以形成包括第一栅极和第二栅极的双栅极结构。

    Method of manufacturing multi-layer metal capacitor
    32.
    发明授权
    Method of manufacturing multi-layer metal capacitor 有权
    制造多层金属电容器的方法

    公开(公告)号：US06200629B1

    公开(公告)日：2001-03-13

    申请号：US09228186

    申请日：1999-01-12

    申请人： Shih-Wei Sun

    发明人： Shih-Wei Sun

    IPC分类号： B05D512

    CPC分类号： H01L21/76897 ,  H01L27/0805 ,  H01L28/55

    摘要： A method for manufacturing a capacitor includes the steps of forming a dielectric layer over a substrate, and then forming at least one contact within the dielectric layer. Next, a first metal layer is formed on the dielectric layer and an electromigration layer is formed on the first metal layer. A patterned capacitor dielectric layer is formed on the electromigration layer in a capacitor area. A second metal layer is then formed over the substrate and defined; a portion of second metal serving as an upper electrode of the capacitor is therefore formed on the electromigration layer. A portion of the second metal layer on the contact serves as a portion of the via of the interconnects. The electromigration layer is self-alignedly patterned when patterning the second metal layer, and a portion of the electromigration layer serves as a lower electrode of the capacitor. The electromigration layer on the contact in the via area is used to prevent electromigration.

    摘要翻译： 制造电容器的方法包括以下步骤：在衬底上形成电介质层，然后在电介质层内形成至少一个接触。 接着，在电介质层上形成第一金属层，在第一金属层上形成电迁移层。 在电容器区域的电迁移层上形成图案化的电容器介电层。 然后在衬底上形成第二金属层并定义; 因此，在电迁移层上形成用作电容器的上电极的第二金属的一部分。 接触件上的第二金属层的一部分用作互连通孔的一部分。 当图案化第二金属层时，电迁移层是自对准图案，并且电迁移层的一部分用作电容器的下电极。 通孔区域上的触点上的电迁移层用于防止电迁移。

    Intermetal dielectric layer formation with low dielectric constant using high density plasma chemical vapor deposition process
    33.
    发明授权
    Intermetal dielectric layer formation with low dielectric constant using high density plasma chemical vapor deposition process 失效
    使用高密度等离子体化学气相沉积工艺，具有低介电常数的金属间介电层形成

    公开(公告)号：US6100205A

    公开(公告)日：2000-08-08

    申请号：US958828

    申请日：1997-10-28

    申请人： Chih-Chien Liu ,  J. Y. Wu ,  Tsang-Jung Lin ,  Water Lur ,  Shih-Wei Sun

    发明人： Chih-Chien Liu ,  J. Y. Wu ,  Tsang-Jung Lin ,  Water Lur ,  Shih-Wei Sun

    IPC分类号： C23C16/04 ,  C23C16/40 ,  C23C16/50 ,  H01L21/316 ,  H01L21/768 ,  H01L21/31

    CPC分类号： H01L21/02164 ,  C23C16/045 ,  C23C16/402 ,  C23C16/50 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/76801

    摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the deposition of dielectric layers using high density plasma chemical vapor deposition (HDPCVD). A first HDPCVD step is carried out to form a first dielectric layer over the wiring lines and into the gaps between wiring lines. A PECVD step is carried out to deposit dielectric material over the first dielectric layer and within and to define a opening in the gap. A second HDPCVD step is carried out and the opening defined by the PECVD step is capped by a third dielectric layer. The method allows air-filled voids to be formed between adjacent metal wiring lines in a highly controlled manner which allows selection of the shape of the voids and precise location of the top of the voids. In addition, the voids are sealed by a denser and more durable material than is typical.

    摘要翻译： 在形成半导体器件时，将介电材料沉积在布线之间的间隙中的方法包括使用高密度等离子体化学气相沉积（HDPCVD）沉积介电层。 执行第一HDPCVD步骤以在布线上形成布线之间的间隙中的第一介电层。 执行PECVD步骤以将电介质材料沉积在第一介电层上并且在间隙内并限定开口。 执行第二HDPCVD步骤，并且由PECVD步骤限定的开口被第三介电层覆盖。 该方法允许以相当可控的方式在相邻的金属布线之间形成空气填充的空隙，这允许选择空隙的形状和空隙的顶部的精确定位。 此外，空隙通过比典型的更致密和更耐用的材料密封。

    Multi-step high density plasma chemical vapor deposition process
    34.
    发明授权
    Multi-step high density plasma chemical vapor deposition process 失效
    多级高密度等离子体化学气相沉积工艺

    公开(公告)号：US5968610A

    公开(公告)日：1999-10-19

    申请号：US959407

    申请日：1997-10-28

    申请人： Chih-Chien Liu ,  Kuen-Jian Chen ,  Yu-Hao Chen ,  J. Y. Wu ,  Water Lur ,  Shih-Wei Sun

    发明人： Chih-Chien Liu ,  Kuen-Jian Chen ,  Yu-Hao Chen ,  J. Y. Wu ,  Water Lur ,  Shih-Wei Sun

    IPC分类号： H01L21/316 ,  H01L21/762 ,  B05D3/06 ,  H01L21/76

    CPC分类号： H01L21/02112 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/76224

    摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the deposition of three oxide layers using high density plasma chemical vapor deposition (HDPCVD). A first HDPCVD step is carried out while keeping the substrate unbiased to form an oxide layer over the lines and in the gap. A second HDPCVD step in which the substrate is biased deposits a second oxide layer over the first oxide layer. During the second HDPCVD step some etching occurs and a portion of the first oxide layer is removed. A third HDPCVD step is carried out at a greater etch and sputtering rate than the second step to complete filling of the gap with dielectric material. The first oxide layer acts to protect the underlying structures from etching damage during the third step. Gaps between wiring lines can be filled with dielectric material without forming voids, even for high aspect ratio gaps.

    摘要翻译： 在形成半导体器件时，将介电材料沉积在布线之间的间隙中的方法包括使用高密度等离子体化学气相沉积（HDPCVD）沉积三个氧化物层。 进行第一HDPCVD步骤，同时保持衬底不偏差以在线和间隙中形成氧化物层。 衬底被偏置的第二HDPCVD步骤在第一氧化物层上沉积第二氧化物层。 在第二HDPCVD步骤期间，发生一些蚀刻，并且去除第一氧化物层的一部分。 以比用第二步骤更大的蚀刻和溅射速率进行第三HDPCVD步骤，以完成用电介质材料填充间隙。 第一氧化物层用于在第三步骤期间保护下面的结构免受蚀刻损伤。 布线之间的间隙可以填充介电材料，而不会形成空隙，即使对于高纵横比的间隙也是如此。

    Method of forming a self-aligned silicide device
    35.
    发明授权
    Method of forming a self-aligned silicide device 失效
    形成自对准硅化物器件的方法

    公开(公告)号：US5874353A

    公开(公告)日：1999-02-23

    申请号：US927321

    申请日：1997-09-11

    申请人： Tony Lin ,  Water Lur ,  Shih-Wei Sun

    发明人： Tony Lin ,  Water Lur ,  Shih-Wei Sun

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28061 ,  H01L29/4925 ,  H01L29/4941

    摘要： A method of forming self-aligned silicide devices which includes providing a silicon substrate having shallow trench isolation regions for defining a device area formed therein; then, forming sequentially a gate oxide layer, a polysilicon layer, a first titanium nitride layer, a titanium silicide layer, a second titanium nitride layer and a silicon nitride layer over the substrate. After a gate electrode is etched out from the above layers, a titanium layer is deposited over the device, and then a self-aligned titanium silicide layer is formed using a heating process. The use of a titanium silicide layer having protective top and bottom titanium nitride layers, compared with a single tungsten silicide layer in a conventional method, provides for a self-aligned silicide device having a rather low gate resistance; being free from narrow width effect of a titanium self-aligned silicide layer; is applicable to self-aligned contact window processes, and avoids the cross-diffusion of doped ions in the polysilicon layer of a dual gate electrode having a tungsten polycide layer.

    摘要翻译： 一种形成自对准硅化物器件的方法，其包括提供具有浅沟槽隔离区域的硅衬底，用于限定其中形成的器件区域; 然后在衬底上依次形成栅氧化层，多晶硅层，第一氮化钛层，硅化钛层，第二氮化钛层和氮化硅层。 在从上述层蚀刻出栅电极之后，在器件上沉积钛层，然后使用加热工艺形成自对准硅化钛层。 与常规方法中的单个硅化钨层相比，使用具有保护性顶部和底部氮化钛层的硅化钛层提供具有相当低的栅极电阻的自对准硅化物器件; 没有钛自对准硅化物层的窄宽度效应; 适用于自对准接触窗工艺，并避免掺杂离子在具有钨多硅化物层的双栅电极的多晶硅层中的交叉扩散。

    Polysilicon CMP process for high-density DRAM cell structures
    36.
    发明授权
    Polysilicon CMP process for high-density DRAM cell structures 失效
    用于高密度DRAM单元结构的多晶硅CMP工艺

    公开(公告)号：US5789290A

    公开(公告)日：1998-08-04

    申请号：US806698

    申请日：1997-02-26

    申请人： Shih-Wei Sun

    发明人： Shih-Wei Sun

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L27/10817

    摘要： Pass transistors are formed on the active device regions of a substrate and a layer of silicon oxide is deposited over the transistors and the surface of the layer of silicon oxide is planarized. A thin layer of silicon nitride is deposited on the oxide layer and then vias are opened through the silicon nitride and silicon oxide layers to expose one of the source/drain regions of each of the pass transistors in the memory array. A layer of polysilicon is deposited so as to extend through the vias, forming polysilicon vertical interconnects in contact with the source/drain regions of the pass transistors and then the layer of polysilicon is patterned to form capacitor bottom plates, with each of the capacitor bottom plates connected to a corresponding source/drain region. A second layer of silicon oxide is deposited to cover the capacitor bottom plates and photolithography is performed to provide a plurality of openings through the second silicon oxide layer to each of the capacitor bottom plates. Polysilicon is deposited to fill each of the openings and chemical mechanical polishing is performed to remove excess polysilicon using the silicon oxide layer as a polish stop. The second oxide layer is stripped to leave the capacitor bottom plates with fins or posts extending vertically from the bottom plates. A capacitor dielectric is then formed over the capacitor bottom electrodes, capacitor upper electrodes are formed, and further processing continues in the conventional manner.

    摘要翻译： 通过晶体管形成在衬底的有源器件区域上，并且氧化硅层沉积在晶体管上，并且氧化硅层的表面被平坦化。 在氧化物层上沉积一薄层氮化硅，然后通过氮化硅和氧化硅层开放通孔，以暴露存储器阵列中每个传输晶体管的源/漏区之一。 沉积多晶硅层以延伸穿过通孔，形成与传导晶体管的源极/漏极区域接触的多晶硅垂直互连，然后将多晶硅层图案化以形成电容器底板，其中每个电容器底部 连接到相应的源/漏区的板。 沉积第二层氧化硅以覆盖电容器底板，并进行光刻以提供穿过第二氧化硅层的多个开口到每个电容器底板。 沉积多晶硅以填充每个开口，并进行化学机械抛光以使用氧化硅层作为抛光停止来除去多余的多余硅。 剥离第二氧化物层以离开电容器底板，其中鳍片或柱从底板垂直延伸。 然后在电容器底部电极上形成电容器电介质，形成电容器上部电极，并且以常规方式继续进行进一步的处理。

    Process for forming a semiconductor device having a metal-semiconductor compound
    37.
    发明授权
    Process for forming a semiconductor device having a metal-semiconductor compound 失效
    用于形成具有金属 - 半导体化合物的半导体器件的工艺

    公开(公告)号：US5545574A

    公开(公告)日：1996-08-13

    申请号：US444980

    申请日：1995-05-19

    申请人： Wei-Ming Chen ,  Shih-Wei Sun ,  Paul G. Y. Tsui

    发明人： Wei-Ming Chen ,  Shih-Wei Sun ,  Paul G. Y. Tsui

    IPC分类号： H01L21/285 ,  H01L21/283

    CPC分类号： H01L21/28518

    摘要： A metal-semiconductor compound (72, 74, 76) is formed after a step that introduces nitrogen into regions (52, 54, 56) of the device (100). In one embodiment, a nitrogen-containing gas is exposed to surfaces (42, 44, 46) before forming a titanium layer (62) is deposited. A one-step anneal is performed to form titanium disilicide regions (72, 72, 76) that are in the C54 phase without thermal agglomeration or forming electrical shorts between the titanium disilicide regions (72, 74, 76).

    摘要翻译： 在将氮引入到装置（100）的区域（52,54,56）中的步骤之后形成金属 - 半导体化合物（72,74,76）。 在一个实施方案中，在形成沉积钛层（62）之前，含氮气体暴露于表面（42,44,46）。 进行一步退火以形成处于C54相的二硅化钛区域（72,72,76），而没有热附聚或在二硅化钛区域（72,74,76）之间形成电短路。