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    Method and apparatus for detecting memory device types
    3.
    发明授权
    Method and apparatus for detecting memory device types 失效
    用于检测存储器件类型的方法和装置

    公开(公告)号：US5974501A

    公开(公告)日：1999-10-26

    申请号：US770611

    申请日：1996-12-19

    申请人： Charles N. Shaver ,  Timothy R. Zinsky ,  Paul J. Broyles ,  John E. Larson

    发明人： Charles N. Shaver ,  Timothy R. Zinsky ,  Paul J. Broyles ,  John E. Larson

    IPC分类号： G06F12/06 ,  G06F12/00

    CPC分类号： G06F12/0684

    摘要： A memory controller and method of operation for detecting different type of dynamic random access memory (DRAM) devices in a computer system. The memory controller has capabilities for improved page hits which cause the row address strobe signals to remain asserted following certain cycles. A mechanism in the memory controller selectably disables column address strobing. Different DRAM types are distinguishable by reading back data previously written to a memory location. Data is written to memory with a cycle causing the memory controller to keep the row address strobes asserted. Column address strobing is disabled. A read back cycle is performed without column address strobing. If data is present, the DRAM is an extended data output (EDO) DRAM. If data is not present, the DRAM is a fast page mode DRAM.

    摘要翻译： 一种用于在计算机系统中检测不同类型的动态随机存取存储器（DRAM）装置的存储器控​​制器和操作方法。 存储器控制器具有改进的页面命中的能力，这使得行地址选通信号在特定周期之后保持置位。 存储器控制器中的机制可选地禁用列地址选通。 通过读回以前写入存储器位置的数据，可以区分不同的DRAM类型。 数据被写入存储器，循环使存储器控制器保持行地址选通。 列地址选通禁用。 在没有列地址选通的情况下执行回读周期。 如果存在数据，则DRAM是扩展数据输出（EDO）DRAM。 如果不存在数据，则DRAM是快速页模式DRAM。

    LOAD BALANCING POWER SUPPLIES
    5.
    发明申请
    LOAD BALANCING POWER SUPPLIES 审中-公开
    负载平衡电源

    公开(公告)号：US20100185879A1

    公开(公告)日：2010-07-22

    申请号：US12357642

    申请日：2009-01-22

    申请人： Charles N. Shaver

    发明人： Charles N. Shaver

    IPC分类号： G06F1/00

    CPC分类号： G06F1/3203 ,  G06F1/263 ,  G06F1/3296

    摘要： In one embodiment, a computer system comprises an enclosure, at least one power supply module in the enclosure, the power supply comprising at least a first power output and a second power output, at least one compute node, comprising an input/output module and logic to generate a power input signal to indicate a power input, and at least one administrative module coupled to the at least one power supply module and the at least one compute node. The administrative module comprises an input/output module, a power supply selector circuit module comprising logic to detect the power input signal generated by the at least one compute node and couple the compute node to one of the first power output or the second power output based at least in part on the power input signal.

    摘要翻译： 在一个实施例中，计算机系统包括外壳，外壳中的至少一个电源模块，所述电源包括至少第一电源输出和第二电源输出，至少一个计算节点，包括输入/​​输出模块和 产生电力输入信号以指示功率输入的逻辑，以及耦合到所述至少一个电源模块和所述至少一个计算节点的至少一个管理模块。 管理模块包括输入/​​输出模块，电源选择器电路模块，其包括用于检测由至少一个计算节点产生的功率输入信号并将计算节点耦合到第一功率输出或第二功率输出之一的逻辑 至少部分地在电源输入信号上。

    Self-modifying synchronization memory address space and protocol for communication between multiple busmasters of a computer system
    6.
    发明授权
    Self-modifying synchronization memory address space and protocol for communication between multiple busmasters of a computer system 失效
    自修改同步存储器地址空间和协议，用于计算机系统的多个总线主机之间的通信

    公开(公告)号：US06446149B1

    公开(公告)日：2002-09-03

    申请号：US09033964

    申请日：1998-03-03

    申请人： Michael P. Moriarty ,  Thomas J. Bonola ,  Craig A. Walrath ,  Charles N. Shaver

    发明人： Michael P. Moriarty ,  Thomas J. Bonola ,  Craig A. Walrath ,  Charles N. Shaver

    IPC分类号： G06F1516

    CPC分类号： G06F15/167

    摘要： A computer system provides a self-modifying synchronization memory address space and protocol for communication between multiple busmasters. In one computer system embodiment, the self-modifying synchronization memory address space is provided in a memory controller embedded in a peripheral device of the computer system such as a bridge that provides central, high speed access by a busmaster to the memory controller without accessing a host bus. The synchronization memory address space includes a set of semaphore memory cells mapped to shared critical resources in the computer system. The semaphore memory cell allows for exclusive access by a busmaster to a shared critical resource by switching itself from an idle state to a busy state responsive to a first read operation by a busmaster. In the busy state of the semaphore memory cell, a busy state is communicated to other busmasters which attempt to read the semaphore memory cell. Ownership of the semaphore memory cell is thus achieved using a single operation by a busmaster. The properties of the self-modifying synchronization memory address space and the semaphore memory cell thus eliminate the need for assertion of a bus locking signal to achieve exclusive access for a busmaster to a shared critical resource. These properties also eliminate the need for host processor intervention in accessing a shared critical resource when a busmaster is a PCI master.

    摘要翻译： 计算机系统为多个总线主机之间的通信提供自修改同步存储器地址空间和协议。 在一个计算机系统实施例中，自修改同步存储器地址空间被提供在嵌入在计算机系统的外围设备中的存储器控​​制器中，例如桥接器，其提供总线主管对存储器控制器的中央，高速访问，而不访问 主机总线。 同步存储器地址空间包括映射到计算机系统中的共享关键资源的一组信号量存储器单元。 信号量存储器单元允许总线主机对共享关键资源进行独占访问，通过将总线自身从空闲状态切换到繁忙状态，由总线主管进行第一次读取操作。 在信号量存储单元的忙碌状态下，忙碌状态被传送给尝试读取信号量存储器单元的其它总线主机。 信号量存储单元的所有权由总线主管使用单一操作实现。 因此，自修改同步存储器地址空间和信号量存储单元的属性消除了对总线锁定信号的断言的需要，以实现对总线主机对共享关键资源的独占访问。 当总线主机是PCI主机时，这些属性还消除了主机处理器干预访问共享关键资源的需要。

    GATE DRIVE VOLTAGE SELECTION FOR A VOLTAGE REGULATOR
    7.
    发明申请
    GATE DRIVE VOLTAGE SELECTION FOR A VOLTAGE REGULATOR 有权
    门极驱动电压选择电压调节器

    公开(公告)号：US20080209236A1

    公开(公告)日：2008-08-28

    申请号：US11680524

    申请日：2007-02-28

    申请人： Charles N. Shaver ,  Howard Leverenz

    发明人： Charles N. Shaver ,  Howard Leverenz

    IPC分类号： G06F1/26

    CPC分类号： G06F1/26 ,  H02M3/156 ,  H02M2001/0032 ,  H02M2001/0045 ,  Y02B70/16

    摘要： A system comprises a load and a voltage regulator. The voltage regulator is configured to select a gate drive signal from among a plurality of input voltages. The voltage regulator is configured to use the selected gate drive signal to turn on a power transistor to produce a regulated voltage for the load.

    摘要翻译： 系统包括负载和电压调节器。 电压调节器被配置为从多个输入电压中选择栅极驱动信号。 电压调节器被配置为使用所选择的栅极驱动信号来接通功率晶体管以产生用于负载的调节电压。

    Signal routing circuit for interchangeable microprocessor socket
    9.
    发明授权
    Signal routing circuit for interchangeable microprocessor socket 失效
    用于可互换微处理器插座的信号路由电路

    公开(公告)号：US5473766A

    公开(公告)日：1995-12-05

    申请号：US298362

    申请日：1994-08-30

    申请人： Charles N. Shaver

    发明人： Charles N. Shaver

    IPC分类号： G06F13/40 ,  G06F13/00

    CPC分类号： G06F13/4068

    摘要： A switching circuit controls the routing of various signals of the computer system to and from the various pins of a microprocessor socket. A microprocessor rests in the socket and can be removed and replaced by another microprocessor. Variations in the pin arrangements of the two processors can be compensated for by appropriately setting the switches on the processor card. The use of 486SX, 487SX and 486DX microprocessors is illustrated in a single socket.

    摘要翻译： 开关电路控制计算机系统的各种信号与微处理器插座的各个引脚的路由。 微处理器位于插座中，可以被另一个微处理器取下并更换。 可以通过适当地设置处理器卡上的开关来补偿两个处理器的引脚布置的变化。 使用486SX，487SX和486DX微处理器在单个插座中进行了说明。