公开(公告)号：US08222127B2

公开(公告)日：2012-07-17

申请号：US12176013

申请日：2008-07-18

Applicant: Eugene P. Marsh ,  Gurtej S. Sandhu

Inventor： Eugene P. Marsh ,  Gurtej S. Sandhu

IPC: H01L21/20 ,  H01L29/66

CPC classification number: H01L51/0558 ,  B82Y10/00 ,  G11C13/025 ,  H01L21/02527 ,  H01L21/02606 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02645 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/7781 ,  H01L29/78 ,  H01L51/0003 ,  H01L51/0048 ,  H01L51/0562

Abstract: A semiconductor structure including nanotubes forming an electrical connection between electrodes is disclosed. The semiconductor structure may include an open volume defined by a lower surface of an electrically insulative material and sidewalls of at least a portion of each of a dielectric material and opposing electrodes. The nanotubes may extend between the opposing electrodes, forming a physical and electrical connection therebetween. The nanotubes may be encapsulated within the open volume in the semiconductor structure. A semiconductor structure including nanotubes forming an electrical connection between source and drain regions is also disclosed. The semiconductor structure may include at least one semiconducting carbon nanotube electrically connected to a source and a drain, a dielectric material disposed over the at least one semiconducting carbon nanotube and a gate dielectric overlying a portion of the dielectric material. Methods of forming the semiconductor structures are also disclosed.

Abstract translation: 公开了一种包括在电极之间形成电连接的纳米管的半导体结构。 半导体结构可以包括由电绝缘材料的下表面限定的开放体积和电介质材料和相对电极中的每一个的至少一部分的侧壁。 纳米管可以在相对的电极之间延伸，在它们之间形成物理和电连接。 纳米管可以封装在半导体结构中的开放体积内。 还公开了包括在源区和漏区之间形成电连接的纳米管的半导体结构。 半导体结构可以包括电连接到源极和漏极的至少一个半导体碳纳米管，设置在至少一个半导体碳纳米管上方的电介质材料和覆盖该介电材料的一部分的栅极电介质。 还公开了形成半导体结构的方法。

公开(公告)号：US08207016B2

公开(公告)日：2012-06-26

申请号：US12855562

申请日：2010-08-12

Applicant: Chandra Mouli ,  Gurtej S. Sandhu

Inventor： Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L21/00

CPC classification number: H01L23/3672 ,  H01L23/367 ,  H01L23/373 ,  H01L23/3733 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/10158 ,  Y10S977/742

Abstract: The invention includes semiconductor packages having grooves within a semiconductor die backside; and includes semiconductor packages utilizing carbon nanostructures (such as, for example, carbon nanotubes) as thermally conductive interface materials. The invention also includes methods of cooling a semiconductor die in which coolant is forced through grooves in a backside of the die, and includes methods of making semiconductor packages.

Abstract translation: 本发明包括在半导体模具背面内具有凹槽的半导体封装; 并且包括使用碳纳米结构（例如，碳纳米管）作为导热界面材料的半导体封装。 本发明还包括冷却半导体管芯的方法，其中冷却剂被迫通过管芯背面的凹槽，并且包括制造半导体封装件的方法。

公开(公告)号：US08199556B2

公开(公告)日：2012-06-12

申请号：US12564265

申请日：2009-09-22

Applicant: Bhaskar Srinivasan ,  Gurtej S. Sandhu

Inventor： Bhaskar Srinivasan ,  Gurtej S. Sandhu

IPC: G11C11/00

CPC classification number: G11C13/004 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0061 ,  G11C2013/0052 ,  G11C2213/72

Abstract: Some embodiments include methods of reading memory cells. The memory cells have a write operation that occurs only if a voltage of sufficient absolute value is applied for a sufficient duration of time; and the reading is conducted with a pulse that is of too short of a time duration to be sufficient for the write operation. In some embodiments, the pulse utilized for the reading may have an absolute value of voltage that is greater than or equal to the voltage utilized for the write operation. In some embodiments, the memory cells may comprise non-ohmic devices; such as memristors and diodes.

Abstract translation: 一些实施例包括读取存储器单元的方法。 存储器单元具有写入操作，只有当足够的绝对值的电压施加足够的持续时间时才发生; 并且读取是用太短的持续时间的脉冲来进行的，以足以用于写入操作。 在一些实施例中，用于读取的脉冲可以具有大于或等于用于写入操作的电压的绝对值。 在一些实施例中，存储器单元可以包括非欧姆器件; 如忆阻器和二极管。

公开(公告)号：US20120088348A1

公开(公告)日：2012-04-12

申请号：US13330973

申请日：2011-12-20

Applicant: Gurtej S. Sandhu

Inventor： Gurtej S. Sandhu

IPC: H01L21/02

CPC classification number: H01L28/91 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/31144 ,  H01L27/10852

Abstract: The invention includes methods of forming reticles configured for imprint lithography, methods of forming capacitor container openings, and methods in which capacitor container openings are incorporated into DRAM arrays. An exemplary method of forming a reticle includes formation of a radiation-imageable layer over a material. A lattice pattern is then formed within the radiation-imageable layer, with the lattice pattern defining a plurality of islands of the radiation-imageable layer. The lattice-patterned radiation-imageable layer is utilized as a mask while subjecting the material under the lattice-patterned layer to an etch which transfers the lattice pattern into the material. The etch forms a plurality of pillars which extend only partially into the material, with the pillars being spaced from one another by gaps. The gaps are subsequently narrowed with a second material which only partially fills the gaps.

Abstract translation: 本发明包括形成用于压印光刻的掩模版的方法，形成电容器容器开口的方法，以及将电容器容器开口并入到DRAM阵列中的方法。 形成掩模版的示例性方法包括在材料上形成可辐射成像层。 然后在可辐射成像层内形成格子图案，其中格子图案限定可辐射成像层的多个岛。 将格子图案的可辐射成像层用作掩模，同时使晶格图案层下的材料经历将晶格图案转移到材料中的蚀刻。 蚀刻形成多个柱，其仅部分地延伸到材料中，柱通过间隙彼此间隔开。 间隙随后仅用部分填充间隙的第二材料变窄。

公开(公告)号：US20120070973A1

公开(公告)日：2012-03-22

申请号：US13305072

申请日：2011-11-28

Applicant: Gurtej S. Sandhu ,  Bhaskar Srinivasan

Inventor： Gurtej S. Sandhu ,  Bhaskar Srinivasan

IPC: H01L21/04

CPC classification number: H01L21/04 ,  H01L27/1021 ,  H01L27/2418 ,  H01L29/1606 ,  H01L45/00

Abstract: Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material, and a second conductive material. Spacers may be formed along opposing sidewalls of the stack, and then an entirety of the sacrificial material may be removed to leave a gap between the first conductive material and the at least one dielectric material. In some embodiments of forming diodes, a layer may be formed over a first conductive material, with the layer containing supports interspersed in sacrificial material. At least one dielectric material may be formed over the layer, and a second conductive material may be formed over the at least one dielectric material. An entirety of the sacrificial material may then be removed.

Abstract translation: 一些实施例包括形成二极管的方法。 可以在第一导电材料上形成堆叠。 堆叠可以按升序包括牺牲材料，至少一种电介质材料和第二导电材料。 间隔物可以沿着堆叠的相对侧壁形成，然后可以去除整个牺牲材料以在第一导电材料和至少一种电介质材料之间留下间隙。 在形成二极管的一些实施例中，可以在第一导电材料上形成层，其中包含支撑体的层散布在牺牲材料中。 可以在该层上形成至少一种介电材料，并且可以在该至少一种电介质材料的上方形成第二导电材料。 然后可以去除整个牺牲材料。

公开(公告)号：US20120068143A1

公开(公告)日：2012-03-22

申请号：US12886283

申请日：2010-09-20

Applicant: John Smythe ,  Gurtej S. Sandhu

Inventor： John Smythe ,  Gurtej S. Sandhu

IPC: H01L45/00 ,  H01L21/16

CPC classification number: H01L45/145 ,  H01L27/2409 ,  H01L27/2472 ,  H01L27/2481

Abstract: Some embodiments include methods of forming memory cells utilizing various arrangements of conductive lines, electrodes and programmable material; with the programmable material containing high k dielectric material directly against multivalent metal oxide. Some embodiments include arrays of memory cells, with the memory cells including programmable material containing high k dielectric material directly against multivalent metal oxide.

Abstract translation: 一些实施例包括利用导电线，电极和可编程材料的各种布置形成存储单元的方法; 其中可编程材料含有高k电介质材料直接抵抗多价金属氧化物。 一些实施例包括存储器单元的阵列，其中存储单元包括直接对抗多价金属氧化物的包含高k电介质材料的可编程材料。

公开(公告)号：US08133664B2

公开(公告)日：2012-03-13

申请号：US12397083

申请日：2009-03-03

Applicant: Scott Sills ,  Gurtej S. Sandhu ,  John Smythe ,  Ming Zhang

Inventor： Scott Sills ,  Gurtej S. Sandhu ,  John Smythe ,  Ming Zhang

IPC: G03F7/26

CPC classification number: H01L21/0274 ,  G03F7/20 ,  G03F7/40 ,  H01L21/0337 ,  H01L21/0338

Abstract: Some embodiments include methods of forming patterns of openings. The methods may include forming spaced features over a substrate. The features may have tops and may have sidewalls extending downwardly from the tops. A first material may be formed along the tops and sidewalls of the features. The first material may be formed by spin-casting a conformal layer of the first material across the features, or by selective deposition along the features relative to the substrate. After the first material is formed, fill material may be provided between the features while leaving regions of the first material exposed. The exposed regions of the first material may then be selectively removed relative to both the fill material and the features to create the pattern of openings.

Abstract translation: 一些实施例包括形成开口图案的方法。 所述方法可以包括在衬底上形成间隔的特征。 特征可以具有顶部并且可以具有从顶部向下延伸的侧壁。 第一材料可以沿着特征的顶部和侧壁形成。 第一材料可以通过将特征上的第一材料的共形层旋转浇铸而形成，或通过相对于基底的特征的选择性沉积来形成。 在形成第一材料之后，可以在特征之间提供填充材料，同时使第一材料的区域暴露。 然后可以相对于填充材料和特征来选择性地去除第一材料的暴露区域以产生开口图案。

公开(公告)号：US08129289B2

公开(公告)日：2012-03-06

申请号：US11543515

申请日：2006-10-05

Applicant: John A. Smythe ,  Gurtej S. Sandhu ,  Brian J. Coppa ,  Shyam Surthi ,  Shuang Meng

Inventor： John A. Smythe ,  Gurtej S. Sandhu ,  Brian J. Coppa ,  Shyam Surthi ,  Shuang Meng

IPC: H01L21/00

CPC classification number: H01L21/3088 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/3086 ,  H01L21/3141 ,  H01L21/31612

Abstract: Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring the pattern to a sacrificial material. Spacer regions are then formed on the vertical surfaces of the transferred pattern following the deposition of a conformal material via atomic layer deposition. The spacer regions, and therefore the reduced features, are then transferred to a semiconductor substrate.

Abstract translation: 公开了通过间距倍增来控制半导体制造期间尺寸减小的特征的关键尺寸的方法。 间距倍增通过通过常规光致抗蚀剂技术图案化掩模结构并随后将图案转移到牺牲材料来实现。 然后通过原子层沉积沉积保形材料之后，在转印图案的垂直表面上形成间隔区。 然后将间隔区域以及因此减小的特征转移到半导体衬底。

公开(公告)号：US20120052662A1

公开(公告)日：2012-03-01

申请号：US13290648

申请日：2011-11-07

Applicant: Eugene P. Marsh ,  Gurtej S. Sandhu

Inventor： Eugene P. Marsh ,  Gurtej S. Sandhu

IPC: H01L21/04 ,  H01B1/04 ,  B82B3/00 ,  B82Y40/00

CPC classification number: B82Y30/00 ,  B82Y40/00 ,  C01B32/17 ,  C01B2202/02 ,  C01B2202/06 ,  C01B2202/22 ,  C01B2202/34 ,  Y10T428/249924 ,  Y10T428/249953 ,  Y10T428/2918

Abstract: A process of forming a semiconductive carbon nanotube structure includes imposing energy on a mixture that contains metallic carbon nanotubes and semiconductive carbon nanotubes under conditions to cause the metallic carbon nanotubes to be digested or to decompose so that they may be separated away from the semiconductive carbon nanotubes.

Abstract translation: 形成半导体碳纳米管结构的方法包括在使金属碳纳米管被消化或分解的条件下在包含金属碳纳米管和半导体碳纳米管的混合物上施加能量，使得它们可以与半导体碳纳米管分离 。

公开(公告)号：US20120051132A1

公开(公告)日：2012-03-01

申请号：US12872368

申请日：2010-08-31

Applicant: Gurtej S. Sandhu ,  Bhaskar Srinivasan

Inventor： Gurtej S. Sandhu ,  Bhaskar Srinivasan

IPC: G11C11/36 ,  G11C11/34

CPC classification number: G11C16/0416 ,  G11C16/0483

Abstract: Memory cell structures and methods are described herein. One or more memory cells include a transistor having a charge storage node, a dielectric material positioned between the charge storage node and a channel region of the transistor, the channel region positioned between a source region and a drain region, and a first electrode of a diode coupled to the charge storage node.