公开(公告)号：US20220215283A1

公开(公告)日：2022-07-07

申请号：US17612151

申请日：2020-05-15

Applicant: Google LLC

Inventor： Charles Neill ,  Anthony Edward Megrant

IPC: G06N10/40 ,  G06F15/82

Abstract: A method is presented, including providing an offset magnetic flux bias to a plurality of superconducting qubits and providing respective control magnetic flux biases, for performing a computation, to the plurality of qubits using a plurality of control lines coupled respectively to each qubit. The qubits are configured such that respective resonance frequencies of the qubits are controlled by the offset magnetic flux bias and the respective control magnetic flux biases. The qubits are arranged to perform the computation when the respective resonance frequencies of the qubits are within an operational dynamic range.

公开(公告)号：US10811276B2

公开(公告)日：2020-10-20

申请号：US16332998

申请日：2016-09-13

Applicant: Google LLC

Inventor： Anthony Edward Megrant

IPC: H01L21/3205 ,  G03F7/09 ,  H01L39/24 ,  H01L39/00 ,  H01L27/18 ,  H01L29/43 ,  H01L21/28 ,  H01L21/768 ,  G03F7/11 ,  C09D133/12 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32 ,  H01L39/12

Abstract: A method includes: providing a device having a first layer and a second layer in contact with a surface of the first layer, in which the second layer includes a first superconductor material; forming a buffer material on the second layer to form an etch buffer layer, in which an etch rate selectivity of the buffer material relative to the second layer upon exposure to a photoresist developer is such that the underlying second layer is not etched during exposure of the buffer layer to the photoresist developer; depositing and removing a selected portion of a resist layer to uncover a first portion of the etch buffer layer, wherein removing the selected portion of the resist layer comprises applying the photoresist developer to the selected portion of the resist layer.

公开(公告)号：US10770638B2

公开(公告)日：2020-09-08

申请号：US16557116

申请日：2019-08-30

Applicant: Google LLC

Inventor： Anthony Edward Megrant

IPC: H01L39/24 ,  H01L39/02 ,  G06N10/00

Abstract: A method includes: providing a first wafer including a first substrate, a first insulator layer on the first substrate, and a first dielectric layer on the first insulator layer; providing a second wafer including a second substrate, a second insulator layer on the second substrate, and a second dielectric layer on the second insulator layer; forming a first superconductor layer on the first dielectric layer; forming a second superconductor layer on the second dielectric layer; joining a surface of the first superconductor layer to a surface of the second superconductor layer to form a wafer stack; and forming a third superconductor layer on exposed first surface of the first dielectric layer.

公开(公告)号：US10770307B2

公开(公告)日：2020-09-08

申请号：US16332998

申请日：2016-09-13

Applicant: Google LLC

Inventor： Anthony Edward Megrant

IPC: H01L21/3205 ,  G03F7/09 ,  H01L39/24 ,  H01L39/00 ,  H01L27/18 ,  H01L29/43 ,  H01L21/28 ,  H01L21/768 ,  G03F7/11 ,  C09D133/12 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32 ,  H01L39/12

Abstract: A method includes: providing a device having a first layer and a second layer in contact with a surface of the first layer, in which the second layer includes a first superconductor material; forming a buffer material on the second layer to form an etch buffer layer, in which an etch rate selectivity of the buffer material relative to the second layer upon exposure to a photoresist developer is such that the underlying second layer is not etched during exposure of the buffer layer to the photoresist developer; depositing and removing a selected portion of a resist layer to uncover a first portion of the etch buffer layer, wherein removing the selected portion of the resist layer comprises applying the photoresist developer to the selected portion of the resist layer.

公开(公告)号：US20190341668A1

公开(公告)日：2019-11-07

申请号：US16462263

申请日：2017-09-13

Applicant: Google LLC

Inventor： Theodore Charles White ,  Anthony Edward Megrant

IPC: H01P7/08 ,  G06N10/00 ,  H01L39/24

Abstract: A device includes: a substrate; a first superconductor layer on the substrate, the first superconductor layer having a first kinetic inductance; and a second superconductor layer on the first superconductor layer, the second superconductor layer having a second kinetic inductance that is lower than the first kinetic inductance, in which the second superconductor layer covers the first superconductor layer such that the second superconductor layer and the first superconductor layer have a same footprint, with the exception of at least a first region where the second superconductor layer is omitted so that the first superconductor layer and the second superconductor layer form a circuit element having a predetermined circuit parameter.

公开(公告)号：US20190259931A1

公开(公告)日：2019-08-22

申请号：US16333505

申请日：2016-09-15

Applicant: Google LLC

Inventor： Anthony Edward Megrant

IPC: H01L39/02 ,  H01L39/24 ,  H01L39/00 ,  G06N10/00

Abstract: A method of fabricating an electrical contact junction that allows current to flow includes: providing a substrate including a first layer of superconductor material; removing a native oxide of the superconductor material of the first layer from a first region of the first layer; forming a capping layer in contact with the first region of the first layer, in which the capping layer prevents reformation of the native oxide of the superconductor material in the first region; forming, after forming the capping layer, a second layer of superconductor material that electrically connects to the first region of the first layer of superconductor material to provide the electrical contact junction that allows current to flow.

公开(公告)号：US12239027B2

公开(公告)日：2025-02-25

申请号：US18117918

申请日：2023-03-06

Applicant: Google LLC

Inventor： Brian James Burkett ,  Ofer Naaman ,  Anthony Edward Megrant ,  Theodore Charles White

IPC: H10N60/01 ,  G06N10/00 ,  H10N60/12 ,  H10N60/80

Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.

公开(公告)号：US20240186143A1

公开(公告)日：2024-06-06

申请号：US18438142

申请日：2024-02-09

Applicant: Google LLC

Inventor： Anthony Edward Megrant

IPC: H01L21/027 ,  G03F7/09 ,  H01L21/3213

CPC classification number: H01L21/0274 ,  G03F7/094 ,  H01L21/32139

Abstract: A method of fabricating a device is presented. The method includes forming a multilayer stack on a substrate which has a principal surface. The multilayer stack includes a supporting layer formed over the principal surface of the substrate and a photoresist layer formed on the supporting layer, patterning the multilayer stack to form at least one opening such that the photoresist layer is undercut by the supporting layer and anisotropically dry etching the substrate.

公开(公告)号：US11751490B2

公开(公告)日：2023-09-05

申请号：US17405373

申请日：2021-08-18

Applicant: Google LLC

Inventor： Anthony Edward Megrant

IPC: H10N60/83 ,  G06N10/00 ,  H10N60/01 ,  H10N69/00 ,  H01L21/768 ,  H10N60/10 ,  H10N60/85 ,  H01L21/285

CPC classification number: H10N60/83 ,  G06N10/00 ,  H10N60/01 ,  H10N69/00 ,  H01L21/2855 ,  H01L21/76891 ,  H10N60/0156 ,  H10N60/0912 ,  H10N60/10 ,  H10N60/855

Abstract: A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.

公开(公告)号：US20230259802A1

公开(公告)日：2023-08-17

申请号：US18005493

申请日：2021-07-14

Applicant: Google LLC

Inventor： Paul \/ictor Klimov ,  Anthony Edward Megrant ,  Andrew Lorne Dunsworth ,  Julian Shaw Kelly

IPC: G06N10/20 ,  G06N10/60

CPC classification number: G06N10/20 ,  G06N10/60

Abstract: A computer-implemented method for simulating quantum hardware performance can include accessing, by a computing system including one or more computing devices, a quantum hardware sample generation model configured to generate quantum hardware samples. The quantum hardware sample generation model can include one or more quantum hardware parameters. The computer-implemented method can include sampling, by the computing system, a quantum hardware sample from the quantum hardware sample generation model. The computer-implemented method can include obtaining, by the computing system, one or more simulated performance measurements based at least in part on the quantum hardware sample.