公开(公告)号：US20180190792A1

公开(公告)日：2018-07-05

申请号：US15397967

申请日：2017-01-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jianwei Peng ,  Hsien-Ching Lo ,  Suresh K. Regonda ,  Edward P. Reis, JR.

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/66636 ,  H01L21/3065 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7851

Abstract: The disclosure is directed to a semiconductor structure and method of forming same. The method including: implanting a species within a region of a substrate adjacent to a gate stack; forming a first spacer laterally adjacent to the gate stack over the substrate; and forming an opening within the implanted region of the substrate, the opening being substantially U-shaped and self-aligned with the first spacer. The semiconductor structure including: a fin; a gate stack substantially surrounding the fin; a first pair of spacers over the fin and laterally adjacent to the gate stack; and a pair of substantially U-shaped cavities within the fin and on opposing sides of the gate stack, the pair of substantially U-shaped cavities being self-aligned with the first pair of spacers, wherein the pair of substantially U-shaped cavities are filled with a source/drain material.

公开(公告)号：US20180151690A1

公开(公告)日：2018-05-31

申请号：US15875055

申请日：2018-01-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tao Han ,  Zhenyu Hu ,  Jinping Liu ,  Hsien-Ching Lo ,  Jianwei Peng

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/0228 ,  H01L29/66795 ,  H01L29/785

Abstract: Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. A first spacer is located adjacent to a vertical sidewall of a gate electrode, a second spacer located between the first spacer and the vertical sidewall of the gate electrode, and a third spacer located between the second spacer and the vertical sidewall of the gate electrode. The first spacer has a higher dielectric constant than the second spacer. The first spacer has a higher dielectric constant than the third spacer. The third spacer has a lower dielectric constant than the second spacer.

公开(公告)号：US09887094B1

公开(公告)日：2018-02-06

申请号：US15585800

申请日：2017-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Jianwei Peng ,  Yanping Shen ,  Hui Zhan

IPC: H01L21/3105 ,  H01L29/66 ,  H01L29/08 ,  H01L21/311

CPC classification number: H01L21/31053 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: One illustrative method disclosed includes, among other things, forming a fin spacer adjacent a lower portion of a fin that is comprised of a fin spacer material, forming a conformal layer of a second spacer material on the exposed sidewalls and the upper surface of the fin, on the fin spacer and adjacent a gate structure of the FinFET device, wherein the second spacer material is a different material than the fin spacer material, performing an etching process to remove the second conformal layer from above the fin spacer to thereby re-expose the sidewalls of the fin above the fin spacer and the upper surface of the fin while forming a gate spacer comprising the second spacer material adjacent the gate structure, and forming an epi semiconductor material on the exposed sidewalls and upper surface of the fins above the first fin spacer.

公开(公告)号：US09577040B2

公开(公告)日：2017-02-21

申请号：US15189079

申请日：2016-06-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peijie Feng ,  Jianwei Peng ,  Yanxiang Liu ,  Shesh Mani Pandey ,  Francis Benistant

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/268 ,  H01L29/10 ,  H01L29/161 ,  H01L29/167 ,  H01L29/417 ,  H01L21/324 ,  H01L29/165

CPC classification number: H01L29/0847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/105 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a source/drain region with an abrupt, vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a gate electrode over and perpendicular to a semiconductor fin; forming first spacers on opposite sides of the gate electrode; forming second spacers on opposite sides of the fin; forming a cavity in the fin adjacent the first spacers, between the second spacers; partially epitaxially growing source/drain regions in each cavity; implanting a first dopant into the partially grown source/drain regions with an optional RTA thereafter; epitaxially growing a remainder of the source/drain regions in the cavities, in situ doped with a second dopant; and implanting a third dopant in the source/drain regions.

Abstract translation: 公开了一种形成具有突然，垂直和共形结的源极/漏极区域的方法以及所得到的器件。 实施例包括在半导体鳍片上方并垂直于半导体鳍片形成栅电极; 在栅电极的相对侧上形成第一间隔物; 在所述翅片的相对侧上形成第二间隔物; 在第二间隔件之间形成邻近第一间隔件的翅片中的空腔; 在每个腔中部分地外延生长源/漏区; 将第一掺杂剂注入部分生长的源极/漏极区域中，其后可选择的RTA; 在空腔中外延生长源/漏区的剩余部分，原位掺杂有第二掺杂剂; 以及在源极/漏极区域中注入第三掺杂剂。

公开(公告)号：US09337306B2

公开(公告)日：2016-05-10

申请号：US14319462

申请日：2014-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jianwei Peng ,  Xusheng Wu ,  Hong Yu ,  Zhao Lun

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/6656 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Approaches for forming an epitaxial (epi) source/drain (S/D) and/or a semiconductor device having an epi S/D are provided. In embodiments of the invention, a first portion of the epi S/D is formed in the S/D region on a fin in a finned substrate. After the first portion is formed, but before completion of the formation of the S/D, a secondary spacer is formed in the S/D region. Then, the remainder portion of the S/D is formed in the S/D region. As a result, the S/D is separated from the gate stack by the secondary spacer.

Abstract translation: 提供了用于形成外延（epi）源极/漏极（S / D）和/或具有外延S / D的半导体器件的方法。 在本发明的实施例中，epi S / D的第一部分形成在鳍状衬底中的翅片上的S / D区域中。 在形成第一部分之后，但在形成S / D之前，在S / D区域中形成二次间隔物。 然后，在S / D区域中形成S / D的剩余部分。 结果，S / D通过辅助间隔件与栅极堆叠分离。