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    ELECTRONIC CIRCUIT FOR ADJUSTING PHASE OF CLOCK
    32.
    发明申请
    ELECTRONIC CIRCUIT FOR ADJUSTING PHASE OF CLOCK 审中-公开

    公开(公告)号：US20200067516A1

    公开(公告)日：2020-02-27

    申请号：US16542469

    申请日：2019-08-16

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： KWANG IL OH ,  Tae Wook KANG ,  Sung Eun KIM ,  Hyuk KIM ,  Mi Jeong PARK ,  Hyung-IL PARK ,  Kyung Jin BYUN ,  Jae-Jin LEE ,  In Gi LIM

    IPC: H03L7/093

    Abstract: The inventive concept includes an oscillating circuit, a phase inverting circuit, and a phase detecting circuit. The oscillating circuit generates a first clock to be used to sample an input signal. The phase inverting circuit outputs a second clock based on the first clock. The phase detecting circuit generates a control signal having a first logic value when a phase difference between a phase of the input signal and a phase of the second clock is less than a reference value for a reference time or more. The phase detecting circuit generates the control signal having a second logic value when the phase difference is equal to or greater than the reference value or when the phase difference is less than the reference value for a time shorter than the reference time. The phase inverting circuit inverts the phase of the second clock when a logic value of the control signal changes from the first logic value to the second logic value or when a logic value of the control signal changes from the second logic value to the first logic value.

    SEMICONDUCTOR DEVICE INCLUDING CMOS CIRCUIT AND OPERATION METHOD THEREOF
    33.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING CMOS CIRCUIT AND OPERATION METHOD THEREOF 审中-公开

    公开(公告)号：US20190245532A1

    公开(公告)日：2019-08-08

    申请号：US16262738

    申请日：2019-01-30

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Tae Wook KANG ,  Jae-Jin LEE ,  Kwang IL OH ,  Sung Eun KIM ,  Sukho LEE ,  Kyuseung HAN

    IPC: H03K17/14 ,  H03K17/08

    CPC classification number: H03K17/145 ,  H03K17/08 ,  H03K2017/0806 ,  H03K2217/0027

    Abstract: The inventive concept relates to a semiconductor device including a CMOS circuit and an operation method thereof. A semiconductor device according to an embodiment of the inventive concept includes a semiconductor circuit, a controller, and a voltage generator. The semiconductor circuit operates at a drive voltage to reduce the delay time between input and output as the temperature increases. The controller determines the malfunction of the CMOS circuit based on the difference between the source-drain current of the PMOS transistor and the source-drain current of the NMOS transistor as the temperature changes. The voltage generator generates or adjusts a body-bias voltage applied to the PMOS transistor or the NMOS transistor based on a malfunction determination of the controller. According to the inventive concept, malfunctions and performance deterioration occurring in a CMOS circuit operating at a low voltage may be reduced.

    NEUROMORPHIC ARITHMETIC DEVICE
    34.
    发明申请
    NEUROMORPHIC ARITHMETIC DEVICE 审中-公开

    公开(公告)号：US20180232635A1

    公开(公告)日：2018-08-16

    申请号：US15804912

    申请日：2017-11-06

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Kwang IL OH ,  Sung Eun KIM ,  Seong Mo PARK ,  Hyung-IL PARK ,  Jae-Jin LEE ,  Joo Hyun LEE

    IPC: G06N3/063 ,  G06F7/68 ,  G06F5/01

    CPC classification number: G06N3/0635 ,  G06F5/01 ,  G06F7/68 ,  H03K19/20

    Abstract: The present disclosure relates to a neuromorphic arithmetic device. The neuromorphic arithmetic device may include first and second synapse circuits, a charging/discharging circuit, a comparator, and a counter. The first synapse circuit may generate a first current by performing a first multiplication operation on a first PWM signal and a first weight, and the second synapse circuit may generate a second current by performing a second multiplication operation on a second PWM signal and a second weight. The charging/discharging circuit may store charges induced by the first current and the second current in a charging period, and may discharge the charges in a discharging period. The comparator may compare a voltage level of the charges discharged in the discharging period and a level of a reference voltage. The counter may count output pulses of an oscillator on the basis of a result of the comparison by the comparator.

    ANOMALY DATA DETECTION DEVICE AND OPERATION METHOD OF THE SAME
    40.
    发明公开
    ANOMALY DATA DETECTION DEVICE AND OPERATION METHOD OF THE SAME 审中-公开

    公开(公告)号：US20240265245A1

    公开(公告)日：2024-08-08

    申请号：US18235919

    申请日：2023-08-21

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Tae Wook KANG ,  Sung Eun KIM ,  Kyung Jin BYUN ,  Kwang Il OH ,  Jae-Jin LEE

    IPC: G06N3/049 ,  G06N3/063

    CPC classification number: G06N3/049 ,  G06N3/063

    Abstract: Disclosed is an anomaly data detection device, which includes a sampler that generates session data including first to m-th sample data based on input data input during a first time interval, a spike signal generator that generates first to m-th spike signals respectively corresponding to the first to m-th sample data based on the session data, a spike neural network that detects whether an output spike fires in at least one output neuron from among output neurons based on the first to m-th spike signals and synaptic weights of each of the output neurons, and a detection circuit that generates a detection signal based on the number of output neurons firing the output spike, and each of the first to m-th spike signals is generated by converting feature information of the corresponding first to m-th sample data into a spike rate code.

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