公开(公告)号：US20190091711A1

公开(公告)日：2019-03-28

申请号：US16140544

申请日：2018-09-25

Applicant: Wei-Jun Wang ,  Ruei-Hong Hong ,  Wen-Yi Chiu ,  Po-Chun Liu ,  Chia-Shin Weng ,  Shi-Kuan Chen

Inventor： Wei-Jun Wang ,  Ruei-Hong Hong ,  Wen-Yi Chiu ,  Po-Chun Liu ,  Chia-Shin Weng ,  Shi-Kuan Chen

IPC: B05B12/00 ,  E03D9/08 ,  G05D7/06

Abstract: A sanitary equipment and a control method thereof are provided. The sanitary equipment includes a main body having an opining, a cover body movably disposed at the main body, an electric motor driving the cover body to move, an auxiliary apparatus disposed at the main body and a control circuit coupled to the electric motor and the auxiliary apparatus. In response to operation or wireless remote control, the control circuit controls the electric motor to drive the cover body to open the opening and turn on the auxiliary apparatus in a first process. In a second process, the control circuit controls the electric motor to drive the cover body to close the opening, and turns off the auxiliary apparatus at the same time. Sequences, numbers of steps of the first process and the second process are different. Accordingly, the sanitary equipment with multiple functions and convenient use is provided.

公开(公告)号：US09233844B2

公开(公告)日：2016-01-12

申请号：US13534368

申请日：2012-06-27

Applicant: Chi-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu

Inventor： Chi-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu

IPC: H01L31/00 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02 ,  H01L29/10 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

CPC classification number: B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/0254 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786

Abstract: The present disclosure is directed to an integrated circuit and a method for the fabrication of the integrated circuit. The integrated circuit includes a lattice matching structure. The lattice matching structure can include a first buffer region, a second buffer region and a superlattice structure formed from AlxGa1-xN/AlyGa1-yN layer pairs.

Abstract translation: 本公开涉及用于制造集成电路的集成电路和方法。 集成电路包括晶格匹配结构。 晶格匹配结构可以包括由Al x Ga 1-x N / Al y Ga 1-y N层对形成的第一缓冲区，第二缓冲区和超晶格结构。

公开(公告)号：US09142407B2

公开(公告)日：2015-09-22

申请号：US13743045

申请日：2013-01-16

Applicant: Chi-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

Inventor： Chi-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/778 ,  H01L29/15 ,  H01L29/20

CPC classification number: H01L21/02507 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/0254 ,  H01L29/157 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/778 ,  H01L29/7787

Abstract: A semiconductor structure includes a substrate, a first III-V compound layer over the substrate, one or more sets of III-V compound layers over the first III-V compound layer, a second III-V compound layer over the one or more sets of III-V compound layers, and an active layer over the second III-V compound layer. The first III-V compound layer has a first type doping. Each of the one or more sets of III-V compound layers includes a lower III-V compound layer and an upper III-V compound layer over the lower III-V compound layer. The upper III-V compound layer having the first type doping, and the lower III-V compound layer is at least one of undoped, unintentionally doped having a second type doping, or doped having the second type doping. The second III-V compound layer is either undoped or unintentionally doped having the second type doping.

Abstract translation: 半导体结构包括衬底，在衬底上的第一III-V化合物层，在第一III-V化合物层上的一组或多组III-V化合物层，在一个或多个组上的第二III-V化合物层 的III-V化合物层，以及在第二III-V化合物层上的活性层。 第一III-V族化合物层具有第一种掺杂。 一组或多组III-V化合物层中的每一个在下III-V化合物层上包括下III-V化合物层和上III-V化合物层。 具有第一类掺杂的上III-V化合物层和下III-V族化合物层是至少一种未掺杂的，无意掺杂的具有第二类型掺杂或掺杂具有第二类掺杂的至少一种。 第二III-V族化合物层是未掺杂的或无意掺杂的，具有第二种掺杂。

公开(公告)号：US20100090312A1

公开(公告)日：2010-04-15

申请号：US12584942

申请日：2009-09-14

Applicant: Yih-Der Guo ,  Suh-Fang Lin ,  Wei-Hung Kuo ,  Po-Chun Liu ,  Tung-Wei Chi ,  Chu-Li Chao ,  Jenq-Dar Tsay

Inventor： Yih-Der Guo ,  Suh-Fang Lin ,  Wei-Hung Kuo ,  Po-Chun Liu ,  Tung-Wei Chi ,  Chu-Li Chao ,  Jenq-Dar Tsay

IPC: H01L29/20 ,  H01L21/20 ,  H01L21/04

CPC classification number: C30B25/02 ,  C23C14/0005 ,  C23C14/021 ,  C23C14/0617 ,  C23C16/01 ,  C23C16/0227 ,  C23C16/303 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/02664 ,  H01L33/0079 ,  H01S2304/12

Abstract: A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes an epitaxy substrate, a nitride pillar layer, a nitride semiconductor layer, and a mask layer. The nitride pillar layer includes a plurality of first patterned arranged pillars and a plurality of second patterned arranged pillars. The nitride pillar layer is formed on the epitaxy substrate. A width of a cross-section of each of the second patterned arranged pillars is smaller than a width of a cross-section of each of the first patterned arranged pillars, and a distance among each of the second patterned arranged pillars is longer than a distance among each of the first patterned arranged pillars. Surfaces of the epitaxy substrate, the first patterned arranged pillars, and the second patterned arranged pillars are covered by the mask layer. The nitride semiconductor layer is formed on the nitride pillar layer.

Abstract translation: 提供一种氮化物半导体衬底及其制造方法。 氮化物半导体衬底包括外延衬底，氮化物衬底层，氮化物半导体层和掩模层。 氮化物柱层包括多个第一图案化排列的柱和多个第二图案化排列的柱。 在外延基板上形成氮化物柱层。 每个第二图案化排列的柱的横截面的宽度小于每个第一图案化排列的柱的横截面的宽度，并且每个第二图案化排列的柱之间的距离长于距离 在每个第一图案化排列的柱子中。 外延衬底的表面，第一图案化排列的柱和第二图案化排列的柱被掩模层覆盖。 氮化物半导体层形成在氮化物柱层上。

公开(公告)号：USD908851S1

公开(公告)日：2021-01-26

申请号：US29669238

申请日：2018-11-06

Applicant: Pin-Hsing Lee ,  Po-Chun Liu ,  Wen-Yi Chiu

Designer： Pin-Hsing Lee ,  Po-Chun Liu ,  Wen-Yi Chiu

公开(公告)号：US20200165859A1

公开(公告)日：2020-05-28

申请号：US16286625

申请日：2019-02-27

Applicant: Ruei-Hong Hong ,  Wen-Yi Chiu ,  Wei-Jun Wang ,  Po-Chun Liu

Inventor： Ruei-Hong Hong ,  Wen-Yi Chiu ,  Wei-Jun Wang ,  Po-Chun Liu

IPC: E05F15/73 ,  E05F15/77 ,  G06T7/20 ,  G06F3/14

Abstract: A space adjustment system and a control method thereof are provided. The space adjustment system includes a body, at least one door leaf, at least one motor, and a control circuit. The door leaf is movably disposed at the body. The door panel of each door leaf includes a panel. The motor can drive the motion of the door leaf. The control circuit is coupled with the panel of the door leaf and motor. The control circuit controls the motor to drive the door leaf, and adjusts the transparency or display function of the panel on the corresponding door leaf in response to a location of the door leaf. Accordingly, multiple space type can be created.

公开(公告)号：US08502190B2

公开(公告)日：2013-08-06

申请号：US13309530

申请日：2011-12-01

Applicant: Po-Chun Liu ,  Chu-Li Chao ,  Yih-Der Guo

Inventor： Po-Chun Liu ,  Chu-Li Chao ,  Yih-Der Guo

IPC: H01L21/00

CPC classification number: H01L33/0079 ,  H01L33/007

Abstract: A LED device is provided. The LED device has a conductive carrier substrate, a light-emitting structure, a plurality of pillar structures, a dielectric layer, a first electrode and a second electrode. The light-emitting structure is located on the conductive carrier substrate. The pillar structures are located on the light-emitting structure. The dielectric layer is to cover a sidewall of the pillar structure. The first electrode is located over the pillar structure, and the second electrode is located on the conductive carrier substrate.

Abstract translation: 提供LED装置。 LED器件具有导电载体衬底，发光结构，多个柱结构，电介质层，第一电极和第二电极。 发光结构位于导电载体基板上。 柱结构位于发光结构上。 电介质层覆盖柱结构的侧壁。 第一电极位于柱结构上方，第二电极位于导电载体基板上。

公开(公告)号：US20120074383A1

公开(公告)日：2012-03-29

申请号：US13309530

申请日：2011-12-01

Applicant: Po-Chun Liu ,  Chu-Li Chao ,  Yih-Der Guo

Inventor： Po-Chun Liu ,  Chu-Li Chao ,  Yih-Der Guo

IPC: H01L33/06

CPC classification number: H01L33/0079 ,  H01L33/007

Abstract: A LED device is provided. The LED device has a conductive carrier substrate, a light-emitting structure, a plurality of pillar structures, a dielectric layer, a first electrode and a second electrode. The light-emitting structure is located on the conductive carrier substrate. The pillar structures are located on the light-emitting structure. The dielectric layer is to cover a sidewall of the pillar structure. The first electrode is located over the pillar structure, and the second electrode is located on the conductive carrier substrate.

Abstract translation: 提供LED装置。 LED器件具有导电载体衬底，发光结构，多个柱结构，电介质层，第一电极和第二电极。 发光结构位于导电载体基板上。 柱结构位于发光结构上。 电介质层覆盖柱结构的侧壁。 第一电极位于柱结构上方，第二电极位于导电载体基板上。

公开(公告)号：US20110156047A1

公开(公告)日：2011-06-30

申请号：US12650465

申请日：2009-12-30

Applicant: Jenq-Dar Tsay ,  Po-Chun Liu

Inventor： Jenq-Dar Tsay ,  Po-Chun Liu

IPC: H01L29/20 ,  H01L21/18 ,  H01L21/20

CPC classification number: H01L21/02639 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/0265 ,  H01L21/02664 ,  H01L21/2007

Abstract: A nitride semiconductor template and a manufacturing method thereof are provided. The nitride semiconductor template includes a carrier substrate with a first thermal expansion coefficient, a nitride semiconductor layer with a second thermal expansion coefficient different from the first thermal expansion coefficient, and a bonding layer. The nitride semiconductor layer disposed on the carrier substrate is at least 10 μm in thickness. A ratio of a dislocation density of the nitride semiconductor layer at a first surface to that at a second surface is from 0.1 to 10. The bonding layer is disposed between the carrier substrate and the nitride semiconductor layer to adhere the nitride semiconductor layer onto the carrier substrate. The second surface is near an interface between the nitride semiconductor layer and the bonding layer, and the first surface is 10 μm from the second surface.

Abstract translation: 提供一种氮化物半导体模板及其制造方法。 氮化物半导体模板包括具有第一热膨胀系数的载体衬底，具有与第一热膨胀系数不同的第二热膨胀系数的氮化物半导体层和结合层。 设置在载体基板上的氮化物半导体层的厚度为10μm以上。 氮化物半导体层在第一表面和第二表面处的位错密度的比率为0.1至10.粘合层设置在载体基板和氮化物半导体层之间，以将氮化物半导体层粘附到载体上 基质。 第二表面靠近氮化物半导体层和接合层之间的界面，第一表面距离第二表面10μm。

公开(公告)号：US20090274883A1

公开(公告)日：2009-11-05

申请号：US12177167

申请日：2008-07-22

Applicant: Po-Chun Liu ,  Yih-Der Guo ,  Tung-Wei Chi ,  Chu-Li Chao

Inventor： Po-Chun Liu ,  Yih-Der Guo ,  Tung-Wei Chi ,  Chu-Li Chao

IPC: B32B3/10 ,  C30B25/04

CPC classification number: C30B25/18 ,  C30B29/403 ,  Y10T428/24802 ,  Y10T428/24851

Abstract: An initial substrate structure for forming a nitride semiconductor substrate is provided. The initial substrate structure includes a substrate, a patterned epitaxial layer, and a mask layer. The patterned epitaxial layer is located on the substrate and is formed by a plurality of pillars. The mask layer is located over the substrate and covers a part of the patterned epitaxial layer. The mask layer includes a plurality of sticks and there is a space between the sticks. The space exposes a portion of an upper surface of the patterned epitaxial layer.

Abstract translation: 提供了用于形成氮化物半导体衬底的初始衬底结构。 初始衬底结构包括衬底，图案化外延层和掩模层。 图案化的外延层位于基板上并且由多个柱形成。 掩模层位于衬底上并覆盖图案化外延层的一部分。 掩模层包括多个棒，并且在棒之间存在空间。 空间暴露图案化外延层的上表面的一部分。