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公开(公告)号：US20190269047A1
公开(公告)日：2019-08-29
申请号：US15761172
申请日：2017-08-31
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Abstract: The present disclosure provides a control unit of display device and a display device. The control unit of display device includes: a back plate a plurality of circuit structures, the plurality of circuit structures being arranged on the back plate; a plurality of electric field shielding structures, each of the electric field shielding structures being arranged between the circuit structures and configured to shield an electric field between the circuit structures, wherein each of the electric field shielding structures includes a plurality of shielding strips, the plurality of shielding strips are spaced apart from each other and projections of the shielding strips a corresponding side of the circuit structure are continuous and uninterrupted.
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公开(公告)号：US20190027498A1
公开(公告)日：2019-01-24
申请号：US15755687
申请日：2017-07-28
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Chunping LONG , Pan LI
IPC: H01L27/12 , G02F1/1343 , G02F1/1368 , G02F1/1339 , G02F1/1362 , G02F1/1333
Abstract: The application discloses an array substrate, comprising a base, a conductive pattern layer disposed on the base, a transparent electrode layer, and an insulating layer disposed between the conductive pattern layer and the transparent electrode layer, the conductive pattern layer comprises a plurality of first conductive patterns, the transparent electrode layer comprises a plurality of transparent electrodes, each of the transparent electrodes is electrically coupled to a corresponding one of the first conductive patterns through a corresponding via hole in the insulating layer, wherein at a position where at least one via hole is located, a stepped structure is formed between the first conductive pattern corresponding to the via hole and the base and/or the insulating layer such that a groove is formed at an upper surface of the array substrate at a position corresponding to the via hole. The application further discloses a display device.
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公开(公告)号：US20180294288A1
公开(公告)日：2018-10-11
申请号：US15512429
申请日：2016-09-02
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Jianbo XIAN , Pan LI
Abstract: An array substrate and a display device are provided. The array substrate includes a display region and a non-display region surrounding the display region. The non-display region includes a connection region where a plurality of connection pads is arranged, and for at least parts of the connection pads, two adjacent connection pads are not overlap each other or partially overlap each other in a first direction.
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公开(公告)号：US20180096956A1
公开(公告)日：2018-04-05
申请号：US15537049
申请日：2016-08-26
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Pan LI , Hongfei CHENG , Yong Qiao , Jian XU , Yongda MA
CPC classification number: H01L23/60 , H01L27/0288 , H01L27/0296 , H01L27/12 , H01L27/124
Abstract: Disclosed are an electrostatic protection structure, array substrate and display device. The electrostatic protection structure includes a first electrostatic protection unit and a second electrostatic protection unit which are disposed in sequence. One end of the first electrostatic protection unit is connected with a first electrostatic beginning end, and another end of the first electrostatic protection unit is connected with an electrostatic discharge end; the second electrostatic protection unit includes a first conduction structure, of which one end is connected with a second electrostatic beginning end and another end is connected with an electrostatic terminating end. The second electrostatic beginning end is a outflow end for static electricity, the first conduction structure is configured to disconnect from the second electrostatic beginning end and/or said electrostatic terminating end when static electricity passes the first conduction structure.
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公开(公告)号：US20160266431A1
公开(公告)日：2016-09-15
申请号：US14769303
申请日：2015-04-10
Applicant: BOE Technology Group Co., Ltd.
Inventor： Wenbo LI , Pan LI , Jianbo XIAN , Hongfei CHENG
IPC: G02F1/1339 , H01L21/285 , G02F1/1368 , H01L29/51 , H01L29/49 , G02F1/1362 , H01L27/12 , H01L21/02
CPC classification number: G02F1/13394 , G02F1/136227 , G02F1/136286 , G02F1/1368 , G02F2001/134345 , H01L21/0217 , H01L21/02274 , H01L21/02532 , H01L21/02565 , H01L21/02592 , H01L21/0262 , H01L21/02631 , H01L21/2855 , H01L27/1222 , H01L27/1225 , H01L27/124 , H01L27/1259 , H01L29/4908 , H01L29/4966 , H01L29/518
Abstract: An array substrate, a display panel and a display apparatus are disclosed. The array substrate includes a plurality of gate lines (10; 50) and a plurality of data lines (30; 51), and pixel units arranged in an array. Each of the pixel units includes one pixel electrode (41; 42) and one thin film transistor, the data line (30; 51) serve as a source electrode (31; 311) of the thin film transistor, the gate line (10; 50) serve as a gate electrode (11) of the thin film transistor, and a drain electrode (32; 321; 322) of the thin film transistor is electrically connected to the pixel electrode (41; 42), at least one of the gate lines (10; 50) and the data lines (30; 51) has a recess (363; 364) provided thereon aligned with a spacer for fixing. With the recess (363; 364), the post spacer is prevented from moving to affect the display region when the substrate is bent and deformed under an external pressure.
Abstract translation: 公开了阵列基板，显示面板和显示装置。 阵列基板包括多条栅线（10; 50）和多条数据线（30; 51），以及排列成阵列的像素单元。 每个像素单元包括一个像素电极（41; 42）和一个薄膜晶体管，数据线（30; 51）用作薄膜晶体管的源电极（31; 311），栅极线（10; 50）用作薄膜晶体管的栅电极（11），并且薄膜晶体管的漏电极（32; 321; 322）电连接到像素电极（41; 42），至少一个 栅线（10; 50）和数据线（30; 51）具有设置在其上的用于固定的间隔件的凹槽（363; 364）。 利用凹部（363,364），当外部压力下基板弯曲和变形时，防止支柱间隔件移动以影响显示区域。
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Patent Agency Ranking
公开(公告)号：US20160252786A1
公开(公告)日：2016-09-01
申请号：US14769690
申请日：2014-12-04
Applicant: BOE Technology Group Co., Ltd.
Inventor： Jianbo XIAN , Yong QIAO , Hongfei CHENG , Wenbo LI , Pan LI
IPC: G02F1/1343 , G02F1/1362
CPC classification number: G02F1/134336 , G02F1/136286 , G02F2001/134318 , G02F2201/121
Abstract: A substrate and a display device are disclosed. The substrate includes a plurality of common electrode lines that are spaced at an interval, configured for providing corresponding pixel units with a common voltage; at least two connecting lines, each of which is located in a display region, and which are configured for achieving mutual electrical connection between at least two of the common electrode lines that are adjacent.
Abstract translation: 公开了一种基板和显示装置。 衬底包括以间隔隔开的多个公共电极线，其被配置为为相应的像素单元提供公共电压; 至少两个连接线，每个连接线位于显示区域中，并且被配置为实现至少两个相邻的公共电极线之间的相互电连接。
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公开(公告)号：US20160197098A1
公开(公告)日：2016-07-07
申请号：US14891086
申请日：2015-04-20
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Jianbo XIAN , Hongfei CHENG , Wenbo LI , Yong QIAO , Pan LI
IPC: H01L27/12
CPC classification number: H01L27/124 , G02F1/136286 , G02F2001/136218 , H01L27/1222 , H01L27/1248 , H01L27/1259
Abstract: An array substrate, a manufacturing method thereof and a display device are provided. The array substrate comprises a plurality of gate lines (102) and a plurality of data lines (101); a region defined by adjacent data lines (101) and adjacent gate lines (102) is a pixel unit; the pixel unit includes a common electrode line (103), a pixel electrode (104), a thin film transistor (105) and an auxiliary electrode (202); a first end of the auxiliary electrode (202) is electrically connected with a drain electrode (203) of the thin film transistor (105); and a second end of the auxiliary electrode (202) is electrically connected with the pixel electrode (104). The array substrate is used for enhancing an electric field within the peripheral range of the pixel electrode (104) of the pixel unit and avoiding the phenomenon of light leakage at an edge of the pixel unit.
Abstract translation: 提供阵列基板，其制造方法和显示装置。 阵列基板包括多条栅线（102）和多条数据线（101）; 由相邻数据线（101）和相邻的栅极线（102）限定的区域是像素单元; 像素单元包括公共电极线（103），像素电极（104），薄膜晶体管（105）和辅助电极（202）。 辅助电极（202）的第一端与薄膜晶体管（105）的漏电极（203）电连接。 并且辅助电极（202）的第二端与像素电极（104）电连接。 阵列基板用于增强像素单元的像素电极（104）的周边范围内的电场，并且避免像素单元的边缘处的光泄漏现象。
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公开(公告)号：US20160147123A1
公开(公告)日：2016-05-26
申请号：US14435923
申请日：2014-09-18
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Hongfei CHENG , Yong QIAO , Jianbo XIAN , Wenbo LI , Pan LI
IPC: G02F1/1362 , G02F1/1343 , H01L27/12 , G02F1/1368
CPC classification number: G02F1/136286 , G02F1/134363 , G02F1/13439 , G02F1/136213 , G02F1/1368 , G02F2001/136218 , H01L27/124
Abstract: An array substrate and a display device are provided. A common electrode line with the same extending direction as a gate line is disposed at one end near a thin film transistor, and forms a storage capacitor with a drain electrode of the thin film transistor. As compared with the case in the prior art that a common electrode line and a thin film transistor in an array substrate are disposed at both ends of a pixel, respectively, and it is necessary to separately provide a storage capacitance electrode useful for forming a storage capacitor with the common electrode line, the pixel region occupied by the thin film transistor and the common electrode line can be effectively decreased. Thus, the aperture ratio is increased, and the display brightness of an IPS liquid crystal display device is enhanced.
Abstract translation: 提供阵列基板和显示装置。 具有与栅极线相同的延伸方向的公共电极线设置在薄膜晶体管附近的一端，并且形成具有薄膜晶体管的漏电极的存储电容器。 与现有技术的情况相比，阵列基板中的公共电极线和薄膜晶体管分别设置在像素的两端，并且需要分开地提供用于形成存储器的辅助电容电极 可以有效地减少具有公共电极线的电容器，由薄膜晶体管占据的像素区域和公共电极线。 因此，开口率增加，IPS液晶显示装置的显示亮度提高。
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公开(公告)号：US20150372016A1
公开(公告)日：2015-12-24
申请号：US14568960
申请日：2014-12-12
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Hongfei CHENG , Wenbo LI , Yong QIAO , Jianbo XIAN , Pan LI
IPC: H01L27/12
CPC classification number: H01L27/124
Abstract: The invention provides an array substrate and a display device. The array substrate comprises a plurality of gate lines and a plurality of data lines which are arranged crosswise and are insulated from each other, and a plurality of pixel units, wherein each pixel unit comprises a control section and a display section, each of which is symmetrically distributed with the central line of a corresponding gate line as a symmetry axis, the control section is located at a cross-point of the gate line and the data line, and is at least partially overlapped with the gate line and the data line, the display section is located at a region defined by the gate line and the data line; and the control section is connected to the display section to control the display section for display. In the present invention, the aperture ratio of the array substrate is increased.
Abstract translation: 本发明提供一种阵列基板和显示装置。 阵列基板包括多个栅极线和交替布置并彼此绝缘的多个数据线，以及多个像素单元，其中每个像素单元包括控制部分和显示部分，每个像素单元是 与对应的栅极线的中心线对称地分布为对称轴，控制部分位于栅极线和数据线的交叉点处，并且至少部分地与栅极线和数据线重叠， 显示部分位于由栅极线和数据线限定的区域中; 并且控制部分连接到显示部分以控制显示部分进行显示。 在本发明中，阵列基板的开口率增大。
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公开(公告)号：US20250113705A1
公开(公告)日：2025-04-03
申请号：US18560169
申请日：2022-11-17
Inventor： Tong WU , Hongli WANG , Pan LI , Ying HAN , Ying CUI , Can YUAN , Xing ZHANG , Ruqin ZHANG , Chunping LONG
IPC: H10K59/121 , H10K59/122 , H10K59/131 , H10K59/88
Abstract: Provided are a display substrate and a display device. The display substrate includes a driving transistor and a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate, the second electrode plate is arranged in a same layer as the channel of the driving transistor, the second electrode plate is closer to the base substrate than the first electrode plate, an orthographic projection of the second electrode plate on the base substrate overlaps with an orthographic projection of the pixel opening on the base substrate, the display substrate satisfies a following relationship: a value range of (W*L+S2)*M1/M2 is [0.014, 0.133], and a value range of S2/(W*L) is [2.82, 28.85], where W is a width of the channel of the driving transistor, L is a length of the channel of the driving transistor, S2 is a facing area between the second electrode plate and the first electrode plate, M1 is a count of pixel openings in the display substrate, and M2 is an area of the display substrate, thus increasing the facing area between the electrode plates of the storage capacitor, increasing the capacitance, and improving the holding capacity of the capacitor, and being beneficial to increasing the area ratio of the storage capacitor to the pixel opening, increasing the area proportion of the storage capacitor, and improving the display quality.
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