公开(公告)号：US20240203743A1

公开(公告)日：2024-06-20

申请号：US18084670

申请日：2022-12-20

Applicant: Applied Materials, Inc.

Inventor： Supakit Charnvanichborikarn ,  Cao-Minh Vincent Lu ,  Ana Cristina Gomez Herrero ,  Hans-Joachim Ludwig Gossmann ,  Wei Zou ,  Andrew Michael Waite

IPC: H01L21/302 ,  C23C14/04 ,  C23C14/48 ,  H01J37/304 ,  H01J37/317 ,  H01L21/02 ,  H01L21/266 ,  H01L21/311

CPC classification number: H01L21/302 ,  C23C14/042 ,  C23C14/48 ,  H01J37/304 ,  H01J37/3171 ,  H01L21/0223 ,  H01L21/266 ,  H01L21/31111

Abstract: A method of processing a semiconductor substrate, including performing a first ion implantation process on the substrate, wherein a first ion beam formed of an ionized first dopant species is directed at a top surface of the substrate and is blocked from a first portion of the substrate while being allowed to implant a second portion of the substrate, and performing a second ion implantation process on the substrate, wherein a second ion beam formed of an ionized second dopant species is directed at the top surface of the substrate and is blocked from the first portion of the substrate while being allowed to implant the second portion of the substrate, wherein an effect of the second ion implantation process on an oxidation rate of the second portion counteracts an effect of the first ion implantation process on the oxidation rate of the second portion.

公开(公告)号：US20240194518A1

公开(公告)日：2024-06-13

申请号：US18079817

申请日：2022-12-12

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Wei Zou

IPC: H01L21/762 ,  H01L21/3115

CPC classification number: H01L21/76224 ,  H01L21/31155

Abstract: Disclosed herein are approaches for forming a shallow trench isolation (STI) to improve extremely thin silicon on insulator (ETSOI) device performance. In one approach, a method may include providing a device stack comprising a buried oxide (BOX) layer in a substrate, patterning a hardmask over the substrate, and forming a plurality of isolation regions in the device stack, wherein the plurality of isolation regions extend through the box layer and the substrate. The method may further include forming a well mask over the device stack, wherein an opening through the well mask exposes a first isolation region of the plurality of isolation regions, and modifying a stress of a material of the first isolation region by implanting the first isolation region of the plurality of isolation regions.

公开(公告)号：US11728383B2

公开(公告)日：2023-08-15

申请号：US17032419

申请日：2020-09-25

Applicant: Applied Materials, Inc.

Inventor： Sipeng Gu ,  Wei Zou ,  Kyu-Ha Shim ,  Qintao Zhang

IPC: H01L29/10 ,  H01L29/76 ,  H01L21/265

CPC classification number: H01L29/1054 ,  H01L21/265 ,  H01L29/7606

Abstract: A P-type field effect transistor (PFET) device and a method for fabricating a PFET device using fully depleted silicon on insulator (FDSOI) technology is disclosed. The method includes introducing germanium into the channel layer using ion implantation. This germanium implant increases the axial stress in the channel layer, improving device performance. This implant may be performed at low temperatures to minimize damage to the crystalline structure. Further, rather than using a long duration, high temperature anneal process, the germanium implanted in the channel layer may be annealed using a laser anneal or a rapid temperature anneal. The implanted regions are re-crystallized using the channel layer that is beneath the gate as the seed layer. In some embodiments, an additional oxide spacer is used to further separate the raised source and drain regions from the gate.

公开(公告)号：US20220406604A1

公开(公告)日：2022-12-22

申请号：US17349599

申请日：2021-06-16

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Wei Zou

IPC: H01L21/265 ,  H01L29/417 ,  H01L29/66

Abstract: Disclosed herein are methods for backside wafer dopant activation using a high-temperature ion implant. In some embodiments, a method may include forming a semiconductor device atop a first main side of a substrate, and performing a high-temperature ion implant to a second main side of the substrate, wherein the first main side of the substrate is opposite the second main side of the substrate. The method may further include performing a second ion implant to the second main side of the substrate to form a collector layer.

公开(公告)号：US11430877B2

公开(公告)日：2022-08-30

申请号：US17098082

申请日：2020-11-13

Applicant: Applied Materials, Inc.

Inventor： Sipeng Gu ,  Baonian Guo ,  Qintao Zhang ,  Wei Zou ,  Kyuha Shim

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/3215 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.

公开(公告)号：US20220223416A1

公开(公告)日：2022-07-14

申请号：US17148006

申请日：2021-01-13

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Wei Zou ,  Hans-Joachim L. Gossmann

IPC: H01L21/04 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/28

Abstract: Disclosed herein are methods for reducing MOSFET trench sidewall surface roughness. In some embodiments, a method includes providing a device structure including a well formed in an epitaxial layer, forming a plurality of trenches through the well and the epitaxial layer, and implanting the device structure to form a treated layer along a sidewall of just an upper portion of the device structure within each of the plurality of trenches. The method may further include etching the device structure to remove the treated layer.

公开(公告)号：US20220157968A1

公开(公告)日：2022-05-19

申请号：US17098082

申请日：2020-11-13

Applicant: Applied Materials, Inc.

Inventor： Sipeng Gu ,  Baonian Guo ,  Qintao Zhang ,  Wei Zou ,  Kyuha Shim

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/3215

Abstract: Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.

公开(公告)号：US20220102500A1

公开(公告)日：2022-03-31

申请号：US17032419

申请日：2020-09-25

Applicant: Applied Materials, Inc.

Inventor： Sipeng Gu ,  Wei Zou ,  Kyu-Ha Shim ,  Qintao Zhang

IPC: H01L29/10 ,  H01L21/265 ,  H01L29/76

Abstract: A P-type field effect transistor (PFET) device and a method for fabricating a PFET device using fully depleted silicon on insulator (FDSOI) technology is disclosed. The method includes introducing germanium into the channel layer using ion implantation. This germanium implant increases the axial stress in the channel layer, improving device performance. This implant may be performed at low temperatures to minimize damage to the crystalline structure. Further, rather than using a long duration, high temperature anneal process, the germanium implanted in the channel layer may be annealed using a laser anneal or a rapid temperature anneal. The implanted regions are re-crystallized using the channel layer that is beneath the gate as the seed layer. In some embodiments, an additional oxide spacer is used to further separate the raised source and drain regions from the gate.

公开(公告)号：US20210050411A1

公开(公告)日：2021-02-18

申请号：US16542667

申请日：2019-08-16

Applicant: APPLIED Materials, Inc.

Inventor： Qintao Zhang ,  Wei Zou

IPC: H01L29/06 ,  H01L21/265

Abstract: Embodiments herein are directed to methods and devices having a stress memorization layer along a side of a substrate. In some embodiments, a method may include providing a substrate having a first main side opposite a second main side, implanting the second main side of the substrate to form an amorphous implant area, forming a stress liner over the second main side of the substrate, and annealing the stress liner to form a stress memorization layer in the amorphous implant area.