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    Harmonic detector of critical path monitors
    31.
    发明授权
    Harmonic detector of critical path monitors 有权
    关键路径监视器的谐波检测器

    公开(公告)号：US09135431B2

    公开(公告)日：2015-09-15

    申请号：US13951763

    申请日：2013-07-26

    Applicant: Apple Inc.

    Inventor： Shu-Yi Yu ,  Timothy R. Paaske

    IPC: G06F1/12 ,  G06F21/50 ,  G06F1/08 ,  G06F21/55

    CPC classification number: G06F21/50 ,  G06F1/04 ,  G06F21/558 ,  G06F21/755

    Abstract: A system for monitoring a clock input signal including a reference clock to be monitored, a flip-flop, a plurality of delay logic blocks, a sampling unit, and a comparison unit. The reference clock may have an expected maximum frequency. The flip-flop may be configured to generate a corresponding clock signal at a reduced frequency compared to the reference clock. The plurality of delay logic blocks may be configured to receive the reduced frequency clock signal and delay the signal for various amounts of time, each less than an expected period of the reference clock. The sampling unit may be configured to sample the signals output from the plurality of delay logic blocks. The comparison unit may be configured to receive the outputs of the flip-flop and the sampling unit and use these outputs to determine if the reference clock is running at an acceptable frequency compared to the expected frequency.

    Abstract translation: 一种用于监视包括要监视的参考时钟，触发器，多个延迟逻辑块，采样单元和比较单元的时钟输入信号的系统。 参考时钟可能具有预期的最大频率。 触发器可以被配置为以与参考时钟相比降低的频率产生对应的时钟信号。 多个延迟逻辑块可以被配置为接收降频时钟信号并将信号延迟各种时间量，每个时间量小于参考时钟的期望周期。 采样单元可以被配置为对从多个延迟逻辑块输出的信号进行采样。 比较单元可以被配置为接收触发器和采样单元的输出，并且使用这些输出来确定参考时钟是否以与预期频率相比在可接受的频率下运行。

    REDUCING LATENCY IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS LINK
    32.
    发明申请
    REDUCING LATENCY IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS LINK 有权
    在外围组件互联互通链接中减少延迟

    公开(公告)号：US20150227476A1

    公开(公告)日：2015-08-13

    申请号：US14691244

    申请日：2015-04-20

    Applicant: Apple Inc.

    Inventor： Michael W. Murphy ,  Joshua P. de Cesare ,  Timothy R. Paaske

    IPC: G06F13/24 ,  G06F1/32

    CPC classification number: G06F13/24 ,  G06F1/3253 ,  Y02D10/151

    Abstract: A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period.

    Abstract translation: 描述了一种用于减少主机和端点之间的外围组件互连快速（PCIe）链路中的延迟的方法和系统。 在所描述的实施例中，使用PCIe链路从端点向主机发出中断。 然后，当中断在主机处于等待状态时，PCIe链路被阻止进入功率节省模式，退出延迟大于预定时间段。

    Embedded Encryption/Secure Memory Management Unit for Peripheral Interface Controller
    33.
    发明申请
    Embedded Encryption/Secure Memory Management Unit for Peripheral Interface Controller 有权
    用于外围接口控制器的嵌入式加密/安全内存管理单元

    公开(公告)号：US20150046702A1

    公开(公告)日：2015-02-12

    申请号：US13963457

    申请日：2013-08-09

    Applicant: Apple Inc.

    Inventor： Timothy R. Paaske ,  David S. Warren ,  Michael J. Smith ,  Diarmuid P. Ross ,  Weihua Mao

    IPC: G06F12/14 ,  H04L9/12

    CPC classification number: G06F12/1408 ,  G06F21/602 ,  G06F21/72 ,  G06F21/85 ,  G06F21/87 ,  G09C1/00 ,  H04L9/12 ,  H04L2209/12

    Abstract: In an embodiment, a peripheral interface controller may include an inline cryptographic engine which may encrypt data being sent over a peripheral interface and decrypt data received from the peripheral interface. The encryption may be transparent to the device connected to the peripheral interface that is receiving/supplying the data. In an embodiment, the peripheral interface controller is included in a system on a chip (SOC) that also includes a memory controller configured to couple to a memory. The memory may be mounted on the SOC in a chip-on-chip or package-on-package configuration. The unencrypted data may be stored in the memory for use by other parts of the SOC (e.g. processors, on-chip peripherals, etc.). The keys used for the encryption/decryption of data may remain within the SOC.

    Abstract translation: 在一个实施例中，外围接口控制器可以包括内联密码引擎，其可以对通过外围接口发送的数据进行加密，并解密从外围接口接收的数据。 加密可能对连接到正在接收/提供数据的外设接口的设备是透明的。 在一个实施例中，外围接口控制器包括在芯片上的系统（SOC）中，该系统还包括被配置为耦合到存储器的存储器控​​制器。 存储器可以以片上芯片或封装的封装形式安装在SOC上。 未加密的数据可以存储在存储器中以供SOC的其他部分使用（例如处理器，片上外设等）。 用于加密/解密数据的密钥可能保留在SOC内。

    Secure public key acceleration
    34.
    发明授权
    Secure public key acceleration 有权

    公开(公告)号：US10853504B1

    公开(公告)日：2020-12-01

    申请号：US16691900

    申请日：2019-11-22

    Applicant: Apple Inc.

    Inventor： Timothy R. Paaske ,  Mitchell D. Adler ,  Conrad Sauerwald ,  Fabrice L. Gautier ,  Shu-Yi Yu

    IPC: G06F21/60 ,  G06F21/62 ,  H04L9/30 ,  G06F21/71 ,  H04L9/32 ,  G09C1/00 ,  H04L9/08 ,  G06F21/32

    Abstract: In an embodiment, a system is provided in which the private key is managed in hardware and is not visible to software. The system may provide hardware support for public key generation, digital signature generation, encryption/decryption, and large random prime number generation without revealing the private key to software. The private key may thus be more secure than software-based versions. In an embodiment, the private key and the hardware that has access to the private key may be integrated onto the same semiconductor substrate as an integrated circuit (e.g. a system on a chip (SOC)). The private key may not be available outside of the integrated circuit, and thus a nefarious third party faces high hurdles in attempting to obtain the private key.

    SYSTEM POWER MANAGEMENT USING COMMUNICATION BUS PROTOCOLS
    35.
    发明申请
    SYSTEM POWER MANAGEMENT USING COMMUNICATION BUS PROTOCOLS 审中-公开

    公开(公告)号：US20200174550A1

    公开(公告)日：2020-06-04

    申请号：US16780817

    申请日：2020-02-03

    Applicant: Apple Inc.

    Inventor： David S. Warren ,  Inna Levit ,  Timothy R. Paaske

    IPC: G06F1/3296 ,  G06F13/42 ,  G06F13/40 ,  G06F1/3206 ,  G06F1/06 ,  G06F1/3237 ,  G06F1/08 ,  G06F1/3234

    Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

    SYSTEMS AND METHODS FOR DETECTING REPLAY ATTACKS ON SECURITY SPACE
    37.
    发明申请
    SYSTEMS AND METHODS FOR DETECTING REPLAY ATTACKS ON SECURITY SPACE 审中-公开

    公开(公告)号：US20190260799A1

    公开(公告)日：2019-08-22

    申请号：US16276504

    申请日：2019-02-14

    Applicant: Apple Inc.

    Inventor： Zhimin Chen ,  Timothy R. Paaske ,  Gilbert H. Herbeck

    IPC: H04L29/06 ,  G06F21/74 ,  G06F21/57 ,  G06F21/71

    Abstract: A system and method for detecting replay attacks on secure data are disclosed. A system on a chip (SOC) includes a security processor. Blocks of data corresponding to sensitive information are stored in off-chip memory. The security processor uses an integrity data structure, such as an integrity tree, for the blocks. The intermediate nodes of the integrity tree use nonces which have been generated independent of any value within a corresponding block. By using only the nonces to generate tags in the root at the top layer stored in on-chip memory and the nodes of the intermediate layers stored in off-chip memory, an amount of storage used is reduced for supporting the integrity tree. When the security processor detects events which create access requests for one or more blocks, the security processor uses the integrity tree to verify a replay attack has not occurred and corrupted data.

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