公开(公告)号：US20200081652A1

公开(公告)日：2020-03-12

申请号：US16129735

申请日：2018-09-12

Applicant: Apple Inc.

Inventor： Lakshmi Narasimha Murthy Nukala ,  Sukalpa Biswas ,  Thejasvi Magudilu Vijavaraj ,  Shane J. Keil ,  Gregory S. Mathews

IPC: G06F3/06 ,  G06F13/16 ,  G06F9/48 ,  G06F9/54

Abstract: A memory controller circuit coupled to multiple memory circuits may receive a read request for a particular one of the memory circuits and insert the read request into one of multiple linked lists that includes a linked list whose entries correspond to previously received read requests and are linked according to respective ages of the read requests. The memory controller circuit may schedule the read request using a head pointer of one of the multiple linked lists.

公开(公告)号：US10175905B2

公开(公告)日：2019-01-08

申请号：US15263833

申请日：2016-09-13

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Liang Deng ,  Kai Lun Hsiung ,  Manu Gulati ,  Rakesh L. Notani ,  Sukalpa Biswas ,  Venkata Ramana Malladi ,  Gregory S. Mathews ,  Enming Zheng ,  Fabien S. Faure

IPC: G06F1/32 ,  G06F3/06 ,  G06F1/08 ,  G06F13/16 ,  G06F13/42

Abstract: Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half. If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.

公开(公告)号：US12093541B1

公开(公告)日：2024-09-17

申请号：US17929925

申请日：2022-09-06

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Jeonghee Shin

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: Techniques are disclosed relating to bandwidth compensation for certain memory traffic at high temperatures. In some embodiments, processor circuitry is configured to execute memory access operations for multiple traffic classes, including a first traffic class (e.g., real-time traffic) associated with a bandwidth quality-of-service parameter and a second traffic class (e.g., low-latency traffic). In some embodiments, memory controller circuitry is configured to access storage circuitry to perform the memory access operations, determine a temperature value associated with the storage circuitry, and, based on detection of a first temperature scenario for the storage circuitry, allocate memory access operations among the first and second traffic class according to a first allocation policy. In some embodiments, in response to detection of a second temperature scenario for the storage circuitry, memory controller circuitry allocates memory access operations among both traffic classes according to a second allocation policy. The second allocation policy may provide greater bandwidth for the first class than the first allocation policy.

公开(公告)号：US20240061617A1

公开(公告)日：2024-02-22

申请号：US18497883

申请日：2023-10-30

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Kai Lun Hsiung ,  Lakshmi Narasimha Murthy Nukala ,  Shane J. Keil ,  Thejasvi Magudilu Vijayaraj ,  Yanzhe Liu ,  Tao Zhang

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F13/1605 ,  G06F3/0644 ,  G06F3/0673

Abstract: Systems, apparatuses, and methods for addressing bank hotspotting are described. A computing system includes a memory controller with an arbiter for determining how to arbitrate access to one or more memory device(s) for received requests. The arbiter categorizes each request in a manner that helps to ensure fair virtual channel distribution across the banks of the memory device(s). The category system includes bank hotspotting functions to give banks that have more requests more chances to go over banks with fewer requests. The category system is implemented proportionally with more category credits given to banks with higher bank depths within the virtual channel.

公开(公告)号：US11829242B2

公开(公告)日：2023-11-28

申请号：US17804932

申请日：2022-06-01

Applicant: Apple Inc.

Inventor： Farid Nemati ,  Steven R. Hutsell ,  Gregory S. Mathews ,  Yi Chun Chen ,  Kevin C. Wong ,  Kalpana Bansal

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1064 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/106

Abstract: Techniques are disclosed relating to improving memory reliability, e.g., in the context of memory circuits with limited reliability features. In some embodiments, memory controller circuitry is configured to communicate with memory circuitry via an interface that supports link error detection. The memory controller circuitry may, based on a corruption indicator, transmit a data and parity combination for the first data block that causes the memory circuitry to detect an uncorrectable write interface error. Subsequent reads of the location may therefore cause an uncorrectable error indication. This may advantageously allow the memory controller circuitry to propagate a corruption indicator as an uncorrectable error in the memory circuit, without requiring additional tracking of the indicator by the memory circuit or memory controller, in some embodiments.

公开(公告)号：US20220357879A1

公开(公告)日：2022-11-10

申请号：US17313811

申请日：2021-05-06

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Kai Lun Hsiung ,  Lakshmi Narasimha Murthy Nukala ,  Shane J. Keil ,  Thejasvi Magudilu Vijayaraj ,  Yanzhe Liu ,  Tao Zhang

IPC: G06F3/06 ,  G06F13/16

Abstract: Systems, apparatuses, and methods for addressing bank hotspotting are described. A computing system includes a memory controller with an arbiter for determining how to arbitrate access to one or more memory device(s) for received requests. The arbiter categorizes each request in a manner that helps to ensure fair virtual channel distribution across the banks of the memory device(s). The category system includes bank hotspotting functions to give banks that have more requests more chances to go over banks with fewer requests. The category system is implemented proportionally with more category credits given to banks with higher bank depths within the virtual channel.

公开(公告)号：US11221798B2

公开(公告)日：2022-01-11

申请号：US16751975

申请日：2020-01-24

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Kai Lun Hsiung ,  Lakshmi Narasimha Murthy Nukala ,  Peter Fu ,  Rakesh L. Notani ,  Sukalpa Biswas ,  Thejasvi Magudilu Vijayaraj ,  Yanzhe Liu ,  Shane J. Keil

IPC: G06F3/06

Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller is configured to transition between read turns and writes turn according to a turn schedule. In some embodiments, the memory controller also receives reports from circuitry requesting memory transactions and determines a current latency tolerance value based on the reports. In some embodiments, the memory controller is configured to switch from a write turn to a read turn prior to a scheduled switch based on the current latency tolerance meeting a threshold value.

公开(公告)号：US20200133905A1

公开(公告)日：2020-04-30

申请号：US16595230

申请日：2019-10-07

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala ,  Thejasvi Magudilu Vijayaraj ,  Sukulpa Biswas

IPC: G06F13/364 ,  G06F13/18 ,  G06F13/16

Abstract: A memory request management system may include a memory device and a memory controller. The memory controller may include a read queue, a write queue, an arbitration circuit, a read credit allocation circuit, and a write credit allocation circuit. The read queue and write queue may store corresponding requests from request streams. The arbitration circuit may send requests from the read queue and write queue to the memory device based on locations of addresses indicated by the requests. The read credit allocation circuit may send an indication of an available read credit to a request stream in response to a read request from the request stream being sent from the read queue to the memory device. The write credit allocation circuit may send an indication of an available write credit to a request stream in response to a write request from the request stream being stored at the write queue.

公开(公告)号：US20200066328A1

公开(公告)日：2020-02-27

申请号：US16109720

申请日：2018-08-22

Applicant: Apple Inc.

Inventor： Peter Fu ,  Gregory S. Mathews ,  Kai Lun Hsuing ,  Shane J. Keil

IPC: G11C11/406

Abstract: A method and apparatus for performing opportunistic refreshes of memory banks is disclosed. Refresh circuitry in a memory controller performs a refresh on each bank of a multi-bank memory at least once during a given refresh interval. At the beginning of an interval, memory banks for which there are no pending transactions (e.g., reads or writes) may be refreshed. During a first portion of the interval, refresh may be skipped for memory banks for which transactions are pending. In a second portion of the interval, refreshes are performed on memory banks that have not been refreshed during the interval, which may cause some memory transactions to be delayed.

公开(公告)号：US20200004700A1

公开(公告)日：2020-01-02

申请号：US16024063

申请日：2018-06-29

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Shane J. Keil ,  Lakshmi Narasimha Nukala

IPC: G06F13/16 ,  G06F13/40 ,  G06F15/167 ,  G06F15/17

Abstract: A system and method for communication link management in a credit-based system is disclosed. In one embodiment, a system includes first and second functional circuit blocks implemented on an integrated circuit and being able to communicate with one another through establishment of source synchronous links. The first functional circuit block includes a write queue for storing data and information regarding write requests sent from the second functional circuit block. The write queue includes credit management circuitry arranged to convey one or more credits to the second functional circuit block responsive to receiving one or more write requests therefrom. Responsive to receiving the one or more credits and in the absence of any pending additional requests, the second functional circuit block may deactivate a link with the first functional circuit block.