公开(公告)号：US20220310448A1

公开(公告)日：2022-09-29

申请号：US17839170

申请日：2022-06-13

Applicant: Applied Materials, Inc.

Inventor： Xin LIU ,  Fei WANG ,  Rui CHENG ,  Abhijit Basu MALLICK ,  Robert Jan VISSER

IPC: H01L21/768 ,  C23C16/01 ,  C23C16/24 ,  C23C16/455 ,  C23C16/46 ,  C23C16/56 ,  H01L21/02 ,  H01L21/3205

Abstract: Embodiments of the present disclosure relate to processes for filling trenches. The process includes depositing a first amorphous silicon layer on a surface of a layer and a second amorphous silicon layer in a portion of a trench formed in the layer, and portions of side walls of the trench are exposed. The first amorphous silicon layer is removed. The process further includes depositing a third amorphous silicon layer on the surface of the layer and a fourth amorphous silicon layer on the second amorphous silicon layer. The third amorphous silicon layer is removed. The deposition/removal cyclic processes may be repeated until the trench is filled with amorphous silicon layers. The amorphous silicon layers form a seamless amorphous silicon gap fill in the trench since the amorphous silicon layers are formed from bottom up.

公开(公告)号：US20200043722A1

公开(公告)日：2020-02-06

申请号：US16514534

申请日：2019-07-17

Applicant: Applied Materials, Inc.

Inventor： Rui CHENG ,  Karthik JANAKIRAMAN ,  Zubin HUANG ,  Diwakar N. KEDLAYA

IPC: H01L21/02 ,  H01L21/033

Abstract: Embodiments of the present disclosure relate to deposition methods for dielectric layers with zero pattern loading characteristics. In one embodiment, the method includes depositing a conformal dielectric layer on the substrate having a patterned area and a blanket area by exposing the substrate to a deposition precursor and a tuning gas simultaneously without the presence of plasma in a process chamber, wherein the deposition precursor is reacted to form a chemical reaction by-product, and the chemical reaction by-product is the same as the tuning gas, and wherein the deposition precursor and the tuning gas are provided at an amount that is more than required for the deposition reaction to occur at the patterned area and the blanket area.

公开(公告)号：US20180294157A1

公开(公告)日：2018-10-11

申请号：US15925976

申请日：2018-03-20

Applicant: Applied Materials, Inc.

Inventor： Rui CHENG ,  Abhijit Basu MALLICK ,  Yihong CHEN

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/027 ,  C23C16/24 ,  C23C16/50 ,  C23C16/56

CPC classification number: H01L21/0337 ,  C23C16/24 ,  C23C16/50 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/0234 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02658 ,  H01L21/02664 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/67017 ,  H01L21/67103 ,  H01L21/67248

Abstract: In one implementation, a method of forming an amorphous silicon layer on a substrate in a processing chamber is provided. The method comprises depositing a predetermined thickness of a sacrificial dielectric layer over a substrate. The method further comprises forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate. The method further comprises performing a plasma treatment to the patterned features. The method further comprises depositing an amorphous silicon layer on the patterned features and the exposed upper surface of the substrate. The method further comprises selectively removing the amorphous silicon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the amorphous silicon layer.

公开(公告)号：US20180286674A1

公开(公告)日：2018-10-04

申请号：US15936751

申请日：2018-03-27

Applicant: Applied Materials, Inc.

Inventor： Pramit MANNA ,  Shishi JIANG ,  Rui CHENG ,  Abhijit Basu MALLICK

IPC: H01L21/02

CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02592 ,  H01L21/02617 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/76224 ,  H01L29/0649

Abstract: Methods for gapfilling semiconductor device features, such as high aspect ratio trenches, with amorphous silicon film are provided. First, a substrate having features formed in a first surface thereof is positioned in a processing chamber. A conformal deposition process is then performed to deposit a conformal silicon liner layer on the sidewalls of the features and the exposed first surface of the substrate between the features. A flowable deposition process is then performed to deposit a flowable silicon layer over the conformal silicon liner layer. A curing process is then performed to increase silicon density of the flowable silicon layer. Methods described herein generally improve overall etch selectivity by the conformal silicon deposition and the flowable silicon deposition two-step process to realize seam-free gapfilling between features with high quality amorphous silicon film.

公开(公告)号：US20170207088A1

公开(公告)日：2017-07-20

申请号：US15398591

申请日：2017-01-04

Applicant: Applied Materials, Inc.

Inventor： Thomas Jongwan KWON ,  Rui CHENG ,  Abhijit Basu MALLICK ,  Er-Xuan PING ,  Jaesoo AHN

IPC: H01L21/033

CPC classification number: H01L21/0338 ,  H01L21/02109 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/11582 ,  H01L28/00

Abstract: Implementations of the present disclosure relate to improved hardmask materials and methods for patterning and etching of substrates. A plurality of hardmasks may be utilized in combination with patterning and etching processes to enable advanced device architectures. In one implementation, a first hardmask and a second hardmask disposed on a substrate having various material layers disposed thereon. The second hardmask may be utilized to pattern the first hardmask during a first etching process. A third hardmask may be deposited over the first and second hardmasks and a second etching process may be utilized to form channels in the material layers.

公开(公告)号：US20160314960A1

公开(公告)日：2016-10-27

申请号：US15094512

申请日：2016-04-08

Applicant: Applied Materials, Inc.

Inventor： Rui CHENG ,  Pramit MANNA ,  Abhijit Basu MALLICK

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/32

CPC classification number: H01L21/0234 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/0332 ,  H01L21/3105 ,  H01L21/32

Abstract: The present disclosure relates to methods for improving adhesion between a hardmask layer and a subsequent layer on the hardmask layer. Particularly, embodiment of the present disclosure relates to methods for improving adhesion between a metal-doped amorphous carbon layer and a mask layer, such as a silicon oxide layer, a silicon nitride layer, or an amorphous silicon layer. One embodiment of the present disclosure includes performing a plasma treatment to the metal-doped amorphous carbon layer.

Abstract translation: 本公开涉及用于改善硬掩模层和硬掩模层上的后续层之间的粘合性的方法。 特别地，本公开的实施方案涉及用于改善金属掺杂非晶碳层和掩模层之间的粘附性的方法，例如氧化硅层，氮化硅层或非晶硅层。 本公开的一个实施方案包括对金属掺杂的无定形碳层进行等离子体处理。