知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

127 条记录 (耗时 0.019 秒)

    INTEGRATED MEMORY DEVICE HAVING COLUMNS HAVING MULTIPLE BIT LINES
    31.
    发明申请
    INTEGRATED MEMORY DEVICE HAVING COLUMNS HAVING MULTIPLE BIT LINES 有权
    具有多个位线的列的集成存储器件

    公开(公告)号：US20110171803A1

    公开(公告)日：2011-07-14

    申请号：US13052728

    申请日：2011-03-21

    申请人： Ronald Kakoschke ,  Thomas Nirschl ,  Danny Shum ,  Klaus Schrüfer

    发明人： Ronald Kakoschke ,  Thomas Nirschl ,  Danny Shum ,  Klaus Schrüfer

    IPC分类号： H01L21/336

    CPC分类号： G11C16/0416 ,  H01L27/115 ,  H01L29/8616

    摘要： A memory device using tunneling field effect transistors (TFET) and buried bit lines is presented. The memory device includes a matrix containing rows and columns of storage cells. Each storage cell contains at least one cell transistor, which in turn contains first doped regions and second doped regions, one of which is a source and the other a drain. The memory device includes word lines, each of which is connected to storage cells of one row and bit lines, each of which is connected to storage cells of one column. The first doped regions are of a different doping type than the second doped regions.

    摘要翻译： 提出了使用隧道场效应晶体管（TFET）和掩埋位线的存储器件。 存储器件包括包含存储单元的行和列的矩阵。 每个存储单元包含至少一个单元晶体管，其又包含第一掺杂区域和第二掺杂区域，其中一个是源极，另一个是漏极区域。 存储器件包括字线，每条字线连接到一行的存储单元和位线，每一行连接到一列的存储单元。 第一掺杂区域具有与第二掺杂区域不同的掺杂类型。

    MEMORY USING TUNNELING FIELD EFFECT TRANSISTORS
    32.
    发明申请
    MEMORY USING TUNNELING FIELD EFFECT TRANSISTORS 有权
    使用隧道场效应晶体管的存储器

    公开(公告)号：US20110089392A1

    公开(公告)日：2011-04-21

    申请号：US12975997

    申请日：2010-12-22

    申请人： Thomas Nirschl

    发明人： Thomas Nirschl

    IPC分类号： H01L45/00 ,  H01L21/8239

    CPC分类号： H01L29/7391 ,  H01L27/228 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148

    摘要： A memory includes a first tunneling field effect transistor including a first drain and a first source, the first drain coupled to a first resistive memory element. The memory includes a second tunneling field effect transistor including a second drain and sharing the first source, the second drain coupled to a second resistive memory element. The memory includes a first region coupled to the first source for providing a source node.

    摘要翻译： 存储器包括第一隧道场效应晶体管，其包括第一漏极和第一源极，第一漏极耦合到第一电阻存储器元件。 存储器包括第二隧道场效应晶体管，其包括第二漏极并共享第一源极，第二漏极耦合到第二电阻存储器元件。 存储器包括耦合到第一源的第一区域，用于提供源节点。

    ELECTRONIC DEVICE WITH A PROGRAMMABLE RESISTIVE ELEMENT AND A METHOD FOR BLOCKING A DEVICE
    33.
    发明申请
    ELECTRONIC DEVICE WITH A PROGRAMMABLE RESISTIVE ELEMENT AND A METHOD FOR BLOCKING A DEVICE 有权
    具有可编程电阻元件的电子设备和用于阻塞器件的方法

    公开(公告)号：US20110069528A1

    公开(公告)日：2011-03-24

    申请号：US12563427

    申请日：2009-09-21

    申请人： Berndt Gammel ,  Thomas Nirschl ,  Gerd Dirscherl ,  Philip Schlazer

    发明人： Berndt Gammel ,  Thomas Nirschl ,  Gerd Dirscherl ,  Philip Schlazer

    IPC分类号： G11C11/00 ,  H03K19/00

    CPC分类号： G11C13/0059 ,  G11C13/0004 ,  G11C13/0069

    摘要： One or more embodiments relate to an electronic device comprising a circuitry and a programmable resistive element. The programmable resistive element comprises a first and a second state, wherein the programmable resistive element is configured to allow switching from the second state into the first state in response to a signal comprising at least a predefined level. The circuitry is configured to provide signals up the predefined level, wherein the circuitry is configured to provide a switch signal to the programmable resistive element, wherein the switch signal causes switching from the first into the second state.

    摘要翻译： 一个或多个实施例涉及包括电路和可编程电阻元件的电子设备。 可编程电阻元件包括第一和第二状态，其中可编程电阻元件被配置为允许响应于包括至少预定义电平的信号从第二状态切换到第一状态。 该电路被配置为提供上述预定义电平的信号，其中电路被配置为向可编程电阻元件提供开关信号，其中开关信号引起从第一状态切换到第二状态。

    MEMORY CELL ARRANGEMENTS
    34.
    发明申请
    MEMORY CELL ARRANGEMENTS 有权
    存储单元安排

    公开(公告)号：US20100271855A1

    公开(公告)日：2010-10-28

    申请号：US12431060

    申请日：2009-04-28

    申请人： Thomas Nirschl ,  Michael Bollu ,  Mayk Roehrich

    发明人： Thomas Nirschl ,  Michael Bollu ,  Mayk Roehrich

    IPC分类号： G11C5/02 ,  G11C5/06

    CPC分类号： H01L27/11565 ,  G11C5/063 ,  G11C7/18 ,  G11C16/0408 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11587

    摘要： In an embodiment, a memory cell arrangement is provided. The memory cell arrangement may include a first memory cell and a second memory cell, a first source/drain line coupled to a first source/drain region of the first memory cell and a second source/drain line coupled to a second source/drain region of the first memory cell, and a third source/drain line coupled to a first source/drain region of the second memory cell and a fourth source/drain line coupled to a second source/drain region of the second memory cell, wherein the third source/drain line is disposed proximate to the second source/drain line, and wherein the third source/drain line is disposed in the same metallization level as the second source/drain line.

    摘要翻译： 在一个实施例中，提供了存储单元布置。 存储单元布置可以包括第一存储单元和第二存储单元，耦合到第一存储单元的第一源极/漏极区域的第一源极/漏极线和耦合到第二源极/漏极区域的第二源极/漏极线 以及耦合到所述第二存储单元的第一源极/漏极区域的第三源极/漏极线以及耦合到所述第二存储器单元的第二源极/漏极区域的第四源极/漏极线，其中所述第三存储器单元的第三源极/ 源极/漏极线设置在第二源极/漏极线附近，并且其中第三源极/漏极线设置在与第二源极/漏极线相同的金属化水平处。

    System and Method for Regulating a Power Supply
    35.
    发明申请
    System and Method for Regulating a Power Supply 有权
    用于调节电源的系统和方法

    公开(公告)号：US20100244791A1

    公开(公告)日：2010-09-30

    申请号：US12409689

    申请日：2009-03-24

    申请人： Thomas Nirschl

    发明人： Thomas Nirschl

    IPC分类号： G05F1/10

    CPC分类号： H02M3/07 ,  G11C5/147

    摘要： In an embodiment, a method for controlling an output voltage of a power supply system is disclosed. The method includes regulating the power supply to a first voltage. After regulating the power supply to a first voltage, the power supply is regulated to a second voltage, which includes changing an input to the power supply system, and altering charge at an output of the power supply system until the output voltage reaches the second output voltage.

    摘要翻译： 在一个实施例中，公开了一种用于控制电源系统的输出电压的方法。 该方法包括将电源调节到第一电压。 在将电源调节到第一电压之后，电源被调节到第二电压，其包括改变对电源系统的输入，以及改变电源系统的输出端的电荷，直到输出电压达到第二输出 电压。

    RESISTIVE MEMORY INCLUDING BIDIRECTIONAL WRITE OPERATION
    38.
    发明申请
    RESISTIVE MEMORY INCLUDING BIDIRECTIONAL WRITE OPERATION 审中-公开
    电阻式存储器，包括双向写操作

    公开(公告)号：US20090027943A1

    公开(公告)日：2009-01-29

    申请号：US11782312

    申请日：2007-07-24

    申请人： Thomas Nirschl ,  Mark Lamorey

    发明人： Thomas Nirschl ,  Mark Lamorey

    IPC分类号： G11C11/00

    CPC分类号： G11C13/00 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/79

    摘要： A memory includes a first electrode, a second electrode, and a resistive memory element coupled between the first electrode and the second electrode. The memory includes a circuit configured to write a data value to the resistive memory element by sequentially applying a first signal from the first electrode to the second electrode and a second signal from the second electrode to the first electrode.

    摘要翻译： 存储器包括耦合在第一电极和第二电极之间的第一电极，第二电极和电阻性存储元件。 存储器包括被配置为通过从第一电极向第二电极顺序施加第一信号和从第二电极到第一电极的第二信号将数据值写入电阻性存储元件的电路。

    FUSE SENSING SCHEME
    39.
    发明申请
    FUSE SENSING SCHEME 有权
    保险丝感应方案

    公开(公告)号：US20090002119A1

    公开(公告)日：2009-01-01

    申请号：US11770956

    申请日：2007-06-29

    申请人： Thomas Nirschl

    发明人： Thomas Nirschl

    IPC分类号： H01H85/30

    CPC分类号： G11C17/18 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A fuse circuit includes a fuse configured for programming a configuration of an integrated circuit device and a resistive element having a known resistance value operably coupled in parallel with the fuse. The fuse and the resistive element form a parallel circuit configured for quickly sensing a state of the fuse in relation to the known value of the resistive element. In one embodiment, the device may further include a sense circuit operably coupled to the parallel circuit combination of the fuse and the resistive element. The sense circuit is configured to sense one of a FUSED state and an UNFUSED state of the fuse, for example, based on a comparison between a reference resistance and a FUSED resistance of the fuse when coupled to the known resistance. The fuse may comprise a programmable fuse, and the resistive element may comprise a MOS transistor.

    摘要翻译： 熔丝电路包括配置用于对集成电路器件的配置进行编程的熔丝和具有可操作地与保险丝并联的已知电阻值的电阻元件。 保险丝和电阻元件形成并联电路，其配置用于相对于电阻元件的已知值快速感测保险丝的状态。 在一个实施例中，该装置还可以包括可操作地耦合到熔丝和电阻元件的并联电路组合的感测电路。 感测电路被配置为例如基于当与已知电阻耦合时的参考电阻和熔断器的FUSED电阻之间的比较来感测熔丝的FUSED状态和UNFUSED状态之一。 保险丝可以包括可编程熔丝，并且电阻元件可以包括MOS晶体管。

    Readout of multi-level storage cells
    40.
    发明申请
    Readout of multi-level storage cells 有权
    读出多级存储单元

    公开(公告)号：US20080239833A1

    公开(公告)日：2008-10-02

    申请号：US11731766

    申请日：2007-03-30

    申请人： Thomas Nirschl ,  Jan Otterstedt

    发明人： Thomas Nirschl ,  Jan Otterstedt

    IPC分类号： G11C7/06

    CPC分类号： G11C11/5642 ,  G11C16/32 ,  G11C2211/5634

    摘要： A multi-level sensing scheme compares the state of a multi-level storage cell with monotonously changing reference states, which are associated to different information values. That particular information value is identified to be the information stored in the multi-level storage cell, which has associated that reference state which, in a changing direction, firstly exceeds the state.

    摘要翻译： 多级感测方案将多级存储单元的状态与单调变化的参考状态进行比较，其与不同的信息值相关联。 该特定信息值被识别为存储在多级存储单元中的信息，其与改变方向上首先超过该状态的参考状态相关联。