公开(公告)号：US06307236B1

公开(公告)日：2001-10-23

申请号：US09155801

申请日：1998-10-06

Applicant: Nozomu Matsuzaki ,  Hiroyuki Mizuno ,  Masashi Horiguchi

Inventor： Nozomu Matsuzaki ,  Hiroyuki Mizuno ,  Masashi Horiguchi

IPC: H01L2972

CPC classification number: H01L21/823857 ,  B82Y99/00 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/0883 ,  H01L29/42364 ,  Y10S438/981 ,  Y10S977/936

Abstract: The present invention is drawn to a semiconductor integrated circuit device employing on the same silicon substrate a plurality of kinds of MOS transistors different in magnitude of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of two power supply units. The control circuit is responsive to receipt of a control signal supplied thereto for controlling the flow of a current either between the source and gate or between the drain and gate of the tunnel-current increased MOS transistor for use with the main circuit in such a way that the current flow is selectively permitted during certain time period and that it is inhibited during another period.

公开(公告)号：US5680066A

公开(公告)日：1997-10-21

申请号：US182699

申请日：1994-01-13

Applicant: Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yuji Yokoyama ,  Nozomu Matsuzaki ,  Tatsumi Yamauchi ,  Yutaka Kobayashi ,  Nobuyuki Gotou ,  Akira Ide ,  Masahiro Yamamura ,  Hideaki Uchida

Inventor： Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yuji Yokoyama ,  Nozomu Matsuzaki ,  Tatsumi Yamauchi ,  Yutaka Kobayashi ,  Nobuyuki Gotou ,  Akira Ide ,  Masahiro Yamamura ,  Hideaki Uchida

IPC: G11C7/10 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H03K5/1534 ,  H03K19/0175 ,  H03K5/153 ,  G01R29/02 ,  H03K3/033

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H03K19/017518 ,  H03K5/1534

Abstract: A semiconductor device which includes at least one of (1) an input buffer circuit formed of an input level converter and a non-inverting buffer circuit and an inverting buffer circuit each including BiCMOS circuitry which effects high-speed operation; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device such as for a memory are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.

Abstract translation: 一种半导体器件，其包括以下中的至少一个：（1）由输入电平转换器和非反相缓冲电路构成的输入缓冲电路和各自包括实现高速操作的BiCMOS电路的反相缓冲电路; （2）由多个逻辑门形成的解码器电路，每个逻辑门由MOS和双极电路的组合组成; （3）包括多端子晶体管的读出放大器电路; （4）信号或地址转换检测器电路，其包括各自接收例如电压幅度的地址信号并且响应于地址信号的电平的变化而输出当前振幅信号的输入电路，以及连接的检测器电路 具有共源共栅放大器，其布置成使得其在其输入处接收电流幅度信号，并且其中共源共栅放大器输入保持在基本上恒定的电压，其中检测电路检测到一个或多个当前幅度信号的转变 并且响应于此产生电压幅度的ATD信号; 以及（5）输出缓冲器电路，其中根据来自响应于ATD信号的时钟发生器的信号来控制诸如存储器的装置的解码器，读出放大器和输出缓冲器。

公开(公告)号：US5091883A

公开(公告)日：1992-02-25

申请号：US552100

申请日：1990-07-13

Applicant: Nozomu Matsuzaki ,  Takashi Akioka ,  Masahiro Iwamura ,  Atushi Hiraishi ,  Tatsumi Yamauchi ,  Yuji Yokoyama ,  Yutaka Kobayashi ,  Hideaki Uchida

Inventor： Nozomu Matsuzaki ,  Takashi Akioka ,  Masahiro Iwamura ,  Atushi Hiraishi ,  Tatsumi Yamauchi ,  Yuji Yokoyama ,  Yutaka Kobayashi ,  Hideaki Uchida

IPC: G11C11/41 ,  G11C5/06 ,  G11C11/401 ,  G11C11/409 ,  H01L27/10

CPC classification number: G11C5/063

Abstract: An input buffer for processing an external signal is provided in one of passways, which is the most closest to a line for equally dividing the whole of a plurality of memory cell blocks longitudinally or laterally into two sections, the passway interposing between the adjacent memory cell blocks of the plurality of memory cell blocks to which a processed signal of the input buffer is transmitted, whereby the length of the signal pass from the input buffer to each memory cell of the memory cell blocks can be shortened. Therefore, since the memory cell or a logic element existing between the input buffer and the memory cell is operated by a pulse of little distortion without delay of time, a access time can be reduced and a processing speed of a microprocessor can be increased. Further, a degree of freedom in designing a system of a memory or the microprocessor is further improved.

Abstract translation: 用于处理外部信号的输入缓冲器被提供在通路中的一个通道中，该通道最靠近用于将多个存储单元块的整体纵向或横向均匀地分成两部分的通道，该通道插入相邻的存储单元 可以缩短输入缓冲器的经处理信号的多个存储单元块的块，从而可以缩短信号从输入缓冲器传递到存储单元块的每个存储单元的长度。 因此，由于存储单元或者存在于输入缓冲器和存储单元之间的逻辑单元在没有时间延迟的情况下由几个失真的脉冲进行操作，所以可以减少访问时间并且可以提高微处理器的处理速度。 此外，进一步提高了设计存储器或微处理器的系统的自由度。

公开(公告)号：US08859344B2

公开(公告)日：2014-10-14

申请号：US13314154

申请日：2011-12-07

Applicant: Yuichi Matsui ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Naoki Yamamoto ,  Hideyuki Matsuoka ,  Tomio Iwasaki

Inventor： Yuichi Matsui ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Naoki Yamamoto ,  Hideyuki Matsuoka ,  Tomio Iwasaki

IPC: H01L21/82 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.

公开(公告)号：US20120077325A1

公开(公告)日：2012-03-29

申请号：US13314154

申请日：2011-12-07

Applicant: YUICHI MATSUI ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Naoki Yamamoto ,  Hideyuki Matsuoka ,  Tomio Iwasaki

Inventor： YUICHI MATSUI ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Naoki Yamamoto ,  Hideyuki Matsuoka ,  Tomio Iwasaki

IPC: H01L21/20

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.

Abstract translation: 由于这种材料对高熔点金属和氧化硅膜具有低粘附性，所以相变存储器的制造过程已经受到硫属化物材料易于分层的问题的困扰。 此外，硫族化物材料具有低的热稳定性，因此在相变存储器的制造过程中倾向于升华。 根据本发明，在硫族化物材料层上和下方形成导电或绝缘粘合剂层以增强其分层强度。 此外，在硫族化物材料层的侧壁上形成由氮化物膜构成的保护膜，以防止硫属化物材料层的升华。

公开(公告)号：US20120074377A1

公开(公告)日：2012-03-29

申请号：US13314165

申请日：2011-12-07

Applicant: YUICHI MATSUI ,  Nozomu MATSUZAKI ,  Norikatsu TAKAURA ,  Naoki YAMAMOTO ,  Hideyuki MATSUOKA ,  Tomio IWASAKI

Inventor： YUICHI MATSUI ,  Nozomu MATSUZAKI ,  Norikatsu TAKAURA ,  Naoki YAMAMOTO ,  Hideyuki MATSUOKA ,  Tomio IWASAKI

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.

公开(公告)号：US08054680B2

公开(公告)日：2011-11-08

申请号：US10852150

申请日：2004-05-25

Applicant: Nozomu Matsuzaki ,  Tetsuya Ishimaru ,  Makoto Mizuno ,  Takashi Hashimoto

Inventor： Nozomu Matsuzaki ,  Tetsuya Ishimaru ,  Makoto Mizuno ,  Takashi Hashimoto

IPC: G11C11/34 ,  G11C7/00 ,  H01L29/792

CPC classification number: G11C16/107 ,  G11C16/3468

Abstract: Memory cells in which an erase and write operation is performed by injecting electrons from a substrate and extracting the electrons into a gate electrode constitute a semiconductor nonvolatile memory device. That is a gate extraction semiconductor nonvolatile memory device. In that device, if an erase bias is applied in a first process of an erase and write operation, memory cells in an overerase condition occur and the charge retention characteristics of such memory cells are degraded. The present invention provides a semiconductor nonvolatile memory device using means for writing all the memory cells in an erase unit before applying the erase bias, and then applying the erase bias.

Abstract translation: 通过从基板注入电子并将电子提取到栅极电极进行擦除和写入操作的存储单元构成半导体非易失性存储器件。 这是一个栅极提取半导体非易失性存储器件。 在该器件中，如果在擦除和写入操作的第一过程中施加擦除偏置，则发生过度过热状态的存储器单元，并且这种存储器单元的电荷保留特性降低。 本发明提供一种半导体非易失性存储器件，其使用在施加擦除偏置之前将所有存储单元写入擦除单元的装置，然后施加擦除偏置。

公开(公告)号：US20110101297A1

公开(公告)日：2011-05-05

申请号：US12987606

申请日：2011-01-10

Applicant: Masahiro MONIWA ,  Nozomu Matsuzaki ,  Riichiro Takemura

Inventor： Masahiro MONIWA ,  Nozomu Matsuzaki ,  Riichiro Takemura

IPC: H01L45/00

CPC classification number: H01L45/144 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

Abstract: A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element.Between MISFET of the region which forms one memory cell, and MISFET which adjoined it, each source of MISFET adjoins in the front surface of a semiconductor substrate, insulating. And the multi-layer structure of a phase change film, and the electric conduction film of specific resistance lower than the specific resistance is formed in the plan view of the front surface of a semiconductor substrate ranging over each source of both MISFET, and a plug and a plug stacked on it. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of a semiconductor substrate, and an electric conduction film sends the current of a parallel direction on the surface of a semiconductor substrate.

Abstract translation: 实现了容易形成相变膜的半导体器件及其制造方法，在使用相变膜作为存储元件时实现高集成度。 在形成一个存储单元的区域的MISFET和与其相邻的MISFET之间，MISFET的每个源极邻接在半导体衬底的前表面中，绝缘。 并且在两个MISFET的每个源上的半导体衬底的前表面的平面图中形成相变膜的多层结构和比电阻率低的电阻率的导电膜，并且插塞 和堆叠在其上的插头。 多层结构用作在半导体衬底的表面上平行延伸并存在的布线，并且导电膜在半导体衬底的表面上发送平行方向的电流。

公开(公告)号：US07864568B2

公开(公告)日：2011-01-04

申请号：US12516690

申请日：2006-12-07

Applicant: Yoshihisa Fujisaki ,  Satoru Hanzawa ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki ,  Norikatsu Takaura

Inventor： Yoshihisa Fujisaki ,  Satoru Hanzawa ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki ,  Norikatsu Takaura

IPC: G11C11/00

CPC classification number: H01L45/144 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2213/75 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233

Abstract: In a semiconductor storage device such as a phase change memory, a technique which can realize high integration is provided. The semiconductor storage device includes a phase change thin film 101 having two stable phases of a crystal state with low electric resistance and an amorphous state with high electric resistance, upper plug electrodes 102 and 103 provided on one side of the phase change thin film 101, a lower electrode 104 provided on the other side of the phase change thin film 101, a selecting transistor 114 whose drain/source terminals are connected to the upper plug electrode 102 and the lower electrode 104, and a selecting transistor 115 whose drain/source terminals are connected to the upper plug electrode 103 and the lower electrode 104, and a first memory cell is configured with the selecting transistor 114 and a phase change region 111 in the phase change thin film 101 sandwiched between the upper plug electrode 102 and the lower electrode 104, and a second memory cell is configured with the selecting transistor 115 and a phase change region 112 in the phase change thin film 101 sandwiched between the upper plug electrode 103 and the lower electrode 104.

Abstract translation: 在诸如相变存储器的半导体存储装置中，提供了可以实现高集成度的技术。 半导体存储装置包括：具有低电阻的晶体状态的两个稳定相和具有高电阻的非晶态的相变薄膜101，设置在相变薄膜101一侧的上部插塞电极102和103， 设置在相变薄膜101的另一侧的下部电极104，漏极/源极端子连接到上部插塞电极102和下部电极104的选择晶体管114，以及选择晶体管115，其漏极/源极端子 连接到上插头电极103和下电极104，并且第一存储单元配置有夹在上插头电极102和下电极之间的相变薄膜101中的选择晶体管114和相变区域111 104，并且第二存储单元配置有夹在b中的相变薄膜101中的选择晶体管115和相变区域112 在上塞电极103和下电极104之间。

公开(公告)号：US07781814B2

公开(公告)日：2010-08-24

申请号：US12153385

申请日：2008-05-19

Applicant: Nozomu Matsuzaki ,  Hiroyuki Mizuno ,  Masashi Horiguchi

Inventor： Nozomu Matsuzaki ,  Hiroyuki Mizuno ,  Masashi Horiguchi

IPC: H01L29/72

CPC classification number: H01L21/823857 ,  B82Y99/00 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/0883 ,  H01L29/42364 ,  Y10S438/981 ,  Y10S977/936

Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.

Abstract translation: 半导体集成电路器件在相同的硅衬底上采用具有在源极和栅极之间或其漏极和栅极之间流动的不同大小的隧道电流的多种MOS晶体管。 这些MOS晶体管包括隧道电流增加的MOS晶体管，其中至少一个用于构成器件的主电路。 多种MOS晶体管还包括隧道电流减少或耗尽的MOS晶体管，其中至少一个用于控制电路。 该控制电路插入在主电路和两个电源单元中的至少一个之间。