公开(公告)号：US20090267211A1

公开(公告)日：2009-10-29

申请号：US12498913

申请日：2009-07-07

Applicant: Hyun-Soo CHUNG ,  In-Young LEE ,  Son-Kwan HWANG ,  Dong-Ho LEE ,  Seong-Deok HWANG

Inventor： Hyun-Soo CHUNG ,  In-Young LEE ,  Son-Kwan HWANG ,  Dong-Ho LEE ,  Seong-Deok HWANG

IPC: H01L23/52 ,  H01L23/538 ,  H01L23/48

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01093 ,  H01L2224/11 ,  H01L2224/05552

Abstract: Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the trench to form a via hole exposing the bottom surface of the connection pad, and forming a connecting device connected to the connection pad through the via hole. The invention provides a wafer level package having reduced thickness, lower fabrication costs, and increased reliability compared to conventional packages.

Abstract translation: 提供了晶片级封装及其制造方法。 在一个实施例中，方法之一包括形成在晶片上具有连接焊盘的半导体芯片，图案化晶片的底表面以在连接焊盘下方形成沟槽，图案化沟槽的底表面以形成通孔， 并且通过通孔形成连接到连接垫的连接装置。 本发明提供了与传统封装相比，具有减小的厚度，较低的制造成本和增加的可靠性的晶片级封装。

公开(公告)号：US20090261474A1

公开(公告)日：2009-10-22

申请号：US12496176

申请日：2009-07-01

Applicant: Hyun-Soo Chung ,  Ho-Jin Lee ,  Dong-Hyun Jang ,  Dong-Ho Lee

Inventor： Hyun-Soo Chung ,  Ho-Jin Lee ,  Dong-Hyun Jang ,  Dong-Ho Lee

IPC: H01L23/488 ,  H01L23/535

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/274 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01079 ,  H01L2924/01087

Abstract: In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.

Abstract translation: 在具有应力消除间隔物的半导体器件封装及其制造方法中，从芯片本体延伸的金属互连指状物提供芯片互连。 金属手指通过应力消除间隔物与芯片的主体隔离。 在一个示例中，这种隔离采取气隙的形式。 在另一个实例中，这种隔离采用弹性体材料的形式。 在这两种情况下，都避免了金属互连指和芯体之间的热膨胀系数的不匹配，从而减轻了与开裂和分层相关的问题，从而提高了器件的产量和器件的可靠性。

公开(公告)号：US20090244450A1

公开(公告)日：2009-10-01

申请号：US12474192

申请日：2009-05-28

Applicant: Young-Joon Rhee ,  Dong-Ho Lee ,  Chung-Hyo Lee

Inventor： Young-Joon Rhee ,  Dong-Ho Lee ,  Chung-Hyo Lee

IPC: G02F1/1335

CPC classification number: G02F1/1362 ,  G02F2001/136222

Abstract: Thin film transistors are formed on a lower substrate, and red, green, blue and transparent color filters are formed thereon. An organic insulating layer is formed on the color filters, and pixel electrodes are formed thereon. A black matrix and a common electrode are formed on an upper substrate facing the lower substrate.

Abstract translation: 薄膜晶体管形成在下基板上，并且在其上形成红，绿，蓝和透明滤色器。 在滤色片上形成有机绝缘层，在其上形成像素电极。 在面向下基板的上基板上形成黑矩阵和公共电极。

公开(公告)号：US07586182B2

公开(公告)日：2009-09-08

申请号：US11289665

申请日：2005-11-28

Applicant: Seung-Duk Baek ,  Sun-Won Kang ,  Sang-Wook Park ,  Dong-Ho Lee ,  Jong-Joo Lee

Inventor： Seung-Duk Baek ,  Sun-Won Kang ,  Sang-Wook Park ,  Dong-Ho Lee ,  Jong-Joo Lee

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/49833 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Aspects of the subject matter described herein relate to a packaged semiconductor die which becomes a component of a finished multi-chip package. The packaged semiconductor die comprises a die substrate, a semiconductor package, and a sealant. The die substrate includes an insulating substrate and a circuit pattern formed on the insulating substrate. The semiconductor package has a semiconductor chip electrically coupled to the circuit pattern that is a known good package and is coupled to the die substrate. The sealant seals the semiconductor package. The packaged semiconductor die utilizes a known good package which has passed a series of package tests.

Abstract translation: 本文描述的主题的方面涉及成为成品多芯片封装的部件的封装半导体管芯。 封装的半导体管芯包括管芯衬底，半导体封装和密封剂。 芯片基板包括绝缘基板和形成在绝缘基板上的电路图案。 半导体封装具有电耦合到电路图案的半导体芯片，该电路图案是已知的良好封装并且耦合到管芯衬底。 密封剂密封半导体封装。 封装的半导体管芯使用已经通过一系列封装测试的已知的良好封装。

公开(公告)号：US07585700B2

公开(公告)日：2009-09-08

申请号：US11424055

申请日：2006-06-14

Applicant: Jung-Jin Kim ,  Young-Hee Song ,  Dong-Ho Lee

Inventor： Jung-Jin Kim ,  Young-Hee Song ,  Dong-Ho Lee

IPC: H01L21/44 ,  H01L21/48

CPC classification number: H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Disclosed herein is a ball grid array (BGA) package stack that is not limited by ball arrangement because it utilizes a foldable circuit substrate, which permits interconnection between upper and lower individual BGA packages. The foldable circuit substrate has three portions. By bending the middle second portion, the foldable circuit substrate is folded in two. In the lower BGA package, an IC chip is attached on and electrically connected to a top surface of the first portion, and external connection terminals such as solder balls are formed on a bottom surface of the first portion. The top surface of the first portion is covered with a molding resin to protect the chip, and the third portion is placed on an upper surface of the molding resin. The upper BGA package is constructed in a similar manner to the lower BGA package as described above. For stacking, the interconnection terminals of the upper BGA package are joined and electrically connected to the third portion of the foldable circuit substrate of the lower BGA package.

Abstract translation: 本文公开了一种球栅阵列（BGA）封装堆叠，其不受球布置的限制，因为它利用可折叠电路基板，其允许上部和下部单个BGA封装之间的互连。 可折叠电路基板具有三个部分。 通过弯曲中间第二部分，可折叠电路基板折叠成两个。 在较低的BGA封装中，IC芯片附着在电连接到第一部分的顶表面上，并且在第一部分的底表面上形成诸如焊球的外部连接端子。 第一部分的顶表面被模制树脂覆盖以保护芯片，并且第三部分被放置在模制树脂的上表面上。 上部BGA封装以与上述较低BGA封装类似的方式构造。 为了堆叠，上部BGA封装的互连端子被接合并电连接到下部BGA封装的可折叠电路基板的第三部分。

公开(公告)号：US07576607B2

公开(公告)日：2009-08-18

申请号：US11968862

申请日：2008-01-03

Applicant: Chang-Ho Lee ,  Ockgoo Lee ,  Jeonghu Han ,  Kyu Hwan An ,  Hyungwook Kim ,  Dong Ho Lee ,  Ki Seok Yang ,  Haksun Kim ,  Joy Laskar

Inventor： Chang-Ho Lee ,  Ockgoo Lee ,  Jeonghu Han ,  Kyu Hwan An ,  Hyungwook Kim ,  Dong Ho Lee ,  Ki Seok Yang ,  Haksun Kim ,  Joy Laskar

IPC: H03F1/00

CPC classification number: H03F1/565 ,  H01F27/2804 ,  H03F3/195 ,  H03F3/211 ,  H03F3/45475 ,  H03F2200/387 ,  H03F2200/391 ,  H03F2200/399 ,  H03F2200/402 ,  H03F2200/451 ,  H03F2200/541 ,  H03F2203/45138 ,  Y10T29/5313

Abstract: Embodiments of the invention may provide for power amplifier systems and methods. The systems and methods may include a power amplifier that generates a first differential output signal and a second differential output signal, a primary winding comprised of a plurality of primary segments, where a first end of each primary segment is connected to a first common input port and a second end of each primary segment is connected to a second common input port, where the first common input port is operative to receive the first differential output signal, and where the second common input port is operative to receive the second differential output signal, and a single secondary winding inductively coupled to the plurality of primary segments.

Abstract translation: 本发明的实施例可以提供功率放大器系统和方法。 系统和方法可以包括产生第一差分输出信号和第二差分输出信号的功率放大器，由多个主要段组成的初级绕组，其中每个主要段的第一端连接到第一公共输入端口 并且每个主要段的第二端连接到第二公共输入端口，其中第一公共输入端口用于接收第一差分输出信号，并且其中第二公共输入端口用于接收第二差分输出信号， 以及电感耦合到所述多个初级段的单个次级绕组。

公开(公告)号：US07560994B1

公开(公告)日：2009-07-14

申请号：US11968852

申请日：2008-01-03

Applicant: Ockgoo Lee ,  Jeonghu Han ,  Kyu Hwan An ,  Hyungwook Kim ,  Dong Ho Lee ,  Ki Seok Yang ,  Chang-Ho Lee ,  Haksun Kim ,  Joy Laskar

Inventor： Ockgoo Lee ,  Jeonghu Han ,  Kyu Hwan An ,  Hyungwook Kim ,  Dong Ho Lee ,  Ki Seok Yang ,  Chang-Ho Lee ,  Haksun Kim ,  Joy Laskar

IPC: H03F3/04

CPC classification number: H03F3/2176 ,  H03F1/223 ,  H03F1/565 ,  H03F3/193 ,  H03F2200/108 ,  H03F2200/387 ,  H03F2200/451 ,  H03F2200/541

Abstract: Example embodiments of the invention may provide systems and methods for a power amplifier. The systems and methods may include a first common-source device having a first source, a first gate, a first drain, and a first body, where the first source is connected to the first body, and wherein the first gate is connected to an input port. The systems and methods may further include a second common-gate device having a second source, a second gate, a second drain, and a second body, where the second source is connected to the first drain, where the second source is further connected to the second body, and where the second drain is connected to an output port.

Abstract translation: 本发明的示例性实施例可以提供功率放大器的系统和方法。 系统和方法可以包括具有第一源，第一栅极，第一漏极和第一主体的第一共源器件，其中第一源极连接到第一主体，并且其中第一栅极连接到 输入端口。 系统和方法还可以包括具有第二源极，第二栅极，第二漏极和第二主体的第二共栅极器件，其中第二源极连接到第一漏极，其中第二源极连接到 第二主体，第二排出口连接到输出端口。

公开(公告)号：US20090174477A1

公开(公告)日：2009-07-09

申请号：US11968862

申请日：2008-01-03

Applicant: Chang-Ho Lee ,  Ockgoo Lee ,  Jeonghu Han ,  Kyu Hwan An ,  Hyungwook Kim ,  Dong Ho Lee ,  Ki Seok Yang ,  Haksun Kim ,  Joy Laskar

Inventor： Chang-Ho Lee ,  Ockgoo Lee ,  Jeonghu Han ,  Kyu Hwan An ,  Hyungwook Kim ,  Dong Ho Lee ,  Ki Seok Yang ,  Haksun Kim ,  Joy Laskar

IPC: H03F1/00

CPC classification number: H03F1/565 ,  H01F27/2804 ,  H03F3/195 ,  H03F3/211 ,  H03F3/45475 ,  H03F2200/387 ,  H03F2200/391 ,  H03F2200/399 ,  H03F2200/402 ,  H03F2200/451 ,  H03F2200/541 ,  H03F2203/45138 ,  Y10T29/5313

Abstract: Embodiments of the invention may provide for power amplifier systems and methods. The systems and methods may include a power amplifier that generates a first differential output signal and a second differential output signal, a primary winding comprised of a plurality of primary segments, where a first end of each primary segment is connected to a first common input port and a second end of each primary segment is connected to a second common input port, where the first common input port is operative to receive the first differential output signal, and where the second common input port is operative to receive the second differential output signal, and a single secondary winding inductively coupled to the plurality of primary segments.

Abstract translation: 本发明的实施例可以提供功率放大器系统和方法。 系统和方法可以包括产生第一差分输出信号和第二差分输出信号的功率放大器，由多个主要段组成的初级绕组，其中每个主要段的第一端连接到第一公共输入端口 并且每个主要段的第二端连接到第二公共输入端口，其中第一公共输入端口用于接收第一差分输出信号，并且其中第二公共输入端口用于接收第二差分输出信号， 以及电感耦合到所述多个初级段的单个次级绕组。

公开(公告)号：US07545027B2

公开(公告)日：2009-06-09

申请号：US11448772

申请日：2006-06-08

Applicant: Hyun-Soo Chung ,  In-Young Lee ,  Dong-Hyeon Jang ,  Myeong-Soon Park ,  Dong-Ho Lee

Inventor： Hyun-Soo Chung ,  In-Young Lee ,  Dong-Hyeon Jang ,  Myeong-Soon Park ,  Dong-Ho Lee

IPC: H01L23/02

CPC classification number: H01L23/3114 ,  H01L23/525 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/10126 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3025

Abstract: A wafer level package may include a semiconductor substrate supporting an electrode pad. A first insulating layer may be provided on the semiconductor substrate. The first insulating layer may include a first opening through which the electrode pad may be exposed. A seed metal layer may be provided on an entire surface of the first insulating layer. A redistribution interconnection metal layer may be provided on the seed metal layer. A second insulating layer may be provided on the redistribution interconnection metal layer. The second insulating layer may have a second opening spaced from the first opening to expose a portion of the redistribution interconnection metal layer. The second insulating layer may surround the redistribution interconnection metal layer. An unwanted portion of seed metal layer may be removed using the second insulating layer as an etch mask.

Abstract translation: 晶片级封装可以包括支撑电极焊盘的半导体衬底。 第一绝缘层可以设置在半导体衬底上。 第一绝缘层可以包括第一开口，电极焊盘可以暴露在第一开口中。 种子金属层可以设置在第一绝缘层的整个表面上。 再分布互连金属层可以设置在种子金属层上。 第二绝缘层可以设置在再分布互连金属层上。 第二绝缘层可以具有与第一开口间隔开的第二开口，以暴露再分布互连金属层的一部分。 第二绝缘层可以包围再分布互连金属层。 可以使用第二绝缘层作为蚀刻掩模去除种子金属层的不需要的部分。

公开(公告)号：US20090108432A1

公开(公告)日：2009-04-30

申请号：US12338905

申请日：2008-12-18

Applicant: Dong-Ho LEE

Inventor： Dong-Ho LEE

IPC: H01L23/498

CPC classification number: H01L25/105 ,  H01L2224/4824 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/15311

Abstract: A stack package of the present invention is made by stacking at least two area array type chip scale packages. Each chip scale package of an adjacent pair of chip scale packages is attached to the other in a manner that the ball land pads of the upper stacked chip scale package face in the opposite direction to those of the lower stacked chip scale package, and the circuit patterns of the upper stacked chip scale package are electrically connected to the those of the lower stacked chip scale package by, for example, connecting boards. Therefore, it is possible to stack not only fan-out type chip scale packages, but to also efficiently stack ordinary area array type chip scale packages.

Abstract translation: 通过堆叠至少两个区域阵列型芯片级封装件来制造本发明的堆叠封装。 相邻的一对芯片级封装的每个芯片级封装以上堆叠芯片级封装的焊盘焊盘与下堆叠芯片尺寸封装的方向相反的方式附接到另一芯片尺寸封装，并且电路 上堆叠芯片级封装的图案通过例如连接板电连接到下堆叠芯片级封装的图案。 因此，不仅可以堆叠扇出式芯片级封装，而且可以有效地堆叠普通区域阵列型芯片级封装。