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公开(公告)号：US20240356786A1
公开(公告)日：2024-10-24
申请号：US18640492
申请日：2024-04-19
Applicant: Microchip Technology Incorporated
Inventor： Johannes G. Ransijn
CPC classification number: H04L25/03057 , H02M3/07 , H03F3/45475 , H03G5/165 , H04L25/4917
Abstract: An apparatus comprises a discrete-time linear equalizer circuit. The discrete-time linear equalizer circuit includes a sample and hold circuitry including multiple switched-capacitor circuits. The multiple switched-capacitor circuits include at least a switched-capacitor circuit of a pre-cursor tap, a switched-capacitor circuit of a cursor tap, and a switched-capacitor circuit of a post-cursor tap. A clock-driven switch circuitry is to switchably couple a capacitor of the switched-capacitor circuit of the pre-cursor tap to a negative signal input over a first time period, a capacitor of the switched-capacitor circuit of the cursor tap to a positive signal input over a second time period, and a capacitor of the switched-capacitor circuit of the post-cursor tap to the negative signal input over a third time period. The clock-driven switch circuitry is to switchably couple the capacitors of the switched-capacitor circuits in parallel over a fourth time period.
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公开(公告)号：US20240333301A1
公开(公告)日：2024-10-03
申请号：US18129991
申请日：2023-04-03
Applicant: Microchip Technology Incorporated
Inventor： Vincent Quiquempoix
IPC: H03M3/00
Abstract: A device and method for sigma-delta modulation may include an input signal and a plurality of integrators. The output of the integrators and a data input may be input to an adder, the sum output to be input to a quantizer to generate a quantized output signal. A reset input to the first integrator may be asserted during a first sample of the quantized output signal to reduce the signal discontinuity at the input of the first integrator, which improves the stability of the sigma-delta modulator.
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公开(公告)号：US20240322843A1
公开(公告)日：2024-09-26
申请号：US18611441
申请日：2024-03-20
Applicant: Microchip Technology Incorporated
Inventor： Diego Felipe Gomes Coelho , Peter Graumann
CPC classification number: H03M13/153 , G06F17/16 , H03M13/1515
Abstract: A method may include generating a first computational circuit of a current iteration of a Berlekamp algorithm, the first computational circuit to determine a Berlekamp discrepancy value at least partially based on a current Error-Locator Polynomial (ELP) and observed syndromes; and generating a second computational circuit of the current iteration of the Berlekamp algorithm, the second computational circuit to determine an intermediate value, the intermediate value useable by one or more first computational circuits of one or more subsequent iterations of the Berlekamp algorithm to determine Berlekamp discrepancy values.
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34.发明公开公开(公告)号：US20240314124A1
公开(公告)日：2024-09-19
申请号：US18603985
申请日：2024-03-13
Applicant: Microchip Technology Incorporated
Inventor： Paolo Trere
IPC: H04L9/40
CPC classification number: H04L63/0869 , H04L63/061
Abstract: An apparatus comprises a computing device including one or more processors, multiple peripheral communication devices of different communication protocol types operably connected to the one or more processors, and a memory to store processor-executable instructions of an application layer protocol stack. The processor-executable instructions are adapted such that, when executed by the one or more processors, cause the one or more processors to perform operations for respective ones of secure communication sessions to be established with respective destination devices via respective ones of the multiple peripheral communication devices. The operations comprise establishing the respective ones of secure communication sessions with the respective destination devices via the respective ones of the multiple peripheral communication devices according to an exchange of messages of a mutual authentication and key exchange protocol that is common to the multiple peripheral communication devices.
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35.发明公开公开(公告)号：US20240288286A1
公开(公告)日：2024-08-29
申请号：US18585873
申请日：2024-02-23
Applicant: Microchip Technology Incorporated
Inventor： Ganesh Shaga , Surendra Akkina , Sudheer Putttapudi
Abstract: An apparatus comprises a support structure, one or more oscillator coils, a first sense coil, and a second sense coil. The one or more oscillator coils have a circular winding pattern around an axis of rotation for a target. The first sense coil has a coil winding pattern arranged around the axis and surrounded by the circular winding pattern of the one or more oscillator coils. The second sense coil has a coil winding pattern arranged around the axis and surrounded by the circular winding pattern of the one or more oscillator coils. The coil winding pattern of the second sense coil offset from the coil winding pattern of the first sense coil by an angle of substantially Φ degrees, where Φ=60°/N, and N is an integer number of pole pairs of the apparatus.
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Patent Agency Ranking
公开(公告)号：US20240283461A1
公开(公告)日：2024-08-22
申请号：US18231371
申请日：2023-08-08
Applicant: Microchip Technology Incorporated
Inventor： Naveen Raj
IPC: H03M1/74
CPC classification number: H03M1/74
Abstract: The disclosure relates to circuitry, systems, and methods for digital-to-analog conversion. In various examples, a corresponding circuitry may comprise a first digital-to-analog conversion circuit to provide a first analog output signal and a second digital-to-analog conversion circuit to provide a second analog output signal. The circuitry may comprise addition circuitry to provide a combined analog output signal from the first analog output signal and the second analog output signal. A first voltage reference circuit, connected with the first digital-to-analog conversion circuit to provide a first reference voltage and a second voltage reference circuit, connected with the second digital-to-analog conversion circuit to provide a second reference voltage may be provided. The first reference voltage and the second reference voltage may differ from each other.
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公开(公告)号：US20240280624A1
公开(公告)日：2024-08-22
申请号：US18444319
申请日：2024-02-16
Applicant: Microchip Technology Incorporated
Inventor： Dixon Chen , Yanzi Xu , Henry Liang , Kevin Yang , Thor Lei Xia , Jiachi Yu
CPC classification number: G01R31/11 , G01R31/083
Abstract: An apparatus may comprise processing circuitry, a first pair of terminals, and a second pair of terminals that are electrically connected to a cable. The processing circuitry may provide a periodic signal including pulses to the first terminal. The duration of each of the pulses may be at least double the time of travel of the pulses along the length of the cable. The processing circuitry may also detect a fault in the cable responsive to a received signal at the second terminal responsive to the periodic signal.
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38.发明授权公开(公告)号：US12015052B2
公开(公告)日：2024-06-18
申请号：US17747302
申请日：2022-05-18
Applicant: Microchip Technology Incorporated
Inventor： Yaojian Leng
IPC: H01L21/768 , H01L23/522 , H01L49/02
CPC classification number: H01L28/91 , H01L21/76838 , H01L23/5226 , H01L28/92
Abstract: A metal-insulator-metal (MIM) capacitor includes a bottom electrode cup, an insulator, and a top electrode. The bottom electrode cup includes a laterally-extending bottom electrode cup base and a bottom electrode cup sidewall extending upwardly from the laterally-extending bottom electrode cup base. The insulator includes an insulator cup formed in an opening defined by the bottom electrode cup, and a rounded insulator flange extending laterally outwardly and curving upwardly from the insulator cup, the rounded insulator flange covering an upper surface of the bottom electrode cup sidewall. The top electrode is formed in an opening defined by the insulator cup. The top electrode is insulated from the upper surface of the bottom electrode cup sidewall by the rounded insulator flange.
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39.发明公开公开(公告)号：US20240195396A1
公开(公告)日：2024-06-13
申请号：US18531232
申请日：2023-12-06
Applicant: Microchip Technology Incorporated
Inventor： Jiachi Yu , Henry Liang , James Ho , Galin I. Ivanov , Kevin Yang , Dixon Chen , Congqing Xiong , Hongming An
IPC: H03K5/1252 , H03K19/20
CPC classification number: H03K5/1252 , H03K19/20 , H03K2005/00019
Abstract: Reducing emissions of predetermined frequencies using delay elements and related apparatuses, methods, and systems are disclosed. An apparatus includes an input terminal to receive a signal, delay elements electrically connected to the input terminal, an output terminal to provide a reduced slew rate signal, and combination circuitry electrically connected to the delay elements and the output terminal. The delay elements provide delayed signals responsive to the received signal. Respective ones of the delayed signals include delayed versions of the received signal. The combination circuitry combines the delayed signals to generate the reduced slew rate signal. Delays associated with the delay elements are chosen to reduce emissions of one or more predetermined frequencies of the reduced slew rate signal as compared to the received signal.
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公开(公告)号：US20240184369A1
公开(公告)日：2024-06-06
申请号：US18369912
申请日：2023-09-19
Applicant: Microchip Technology Incorporated
Inventor： Razvan Costache
Abstract: A device includes a receiver to receive an input audio signal and output a received audio signal, and signal conversion circuitry to apply a frequency-dependent adjustment to the received audio signal to convert the received audio signal to a haptic signal for use by a haptic actuator.
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