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公开(公告)号：US10110167B2
公开(公告)日：2018-10-23
申请号：US15360333
申请日：2016-11-23
发明人： Yo-Sheng Lin , Hou-Ju Pan , Shao-Chun Liao
摘要： A down-conversion mixer includes a transconductance unit, a resonant unit and a mixing unit. The transconductance unit converts a differential input voltage signal pair into a differential input current signal pair. The resonant unit provides a negative resistance and a differential auxiliary current signal pair. The mixing unit mixes a combination of the differential input current signal pair and the differential auxiliary current signal pair with a differential oscillatory voltage signal pair to generate a differential mixed voltage signal pair.
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公开(公告)号：US09948239B2
公开(公告)日：2018-04-17
申请号：US15272124
申请日：2016-09-21
发明人： Kiyong Choi , Yi Zeng , Hong Sun Kim , Sasha Vujcic , Chirag Dipak Patel , Aleksandar Miodrag Tasic , Timothy Donald Gathman , Wu-Hsin Chen , Klaas van Zalinge
CPC分类号： H03D7/1458 , H03D7/1441 , H03D7/1466 , H03F3/193 , H03F3/21 , H03F3/265 , H03F3/72 , H03F2200/09 , H03F2200/294 , H03F2200/451 , H03F2200/537 , H03F2200/541 , H03G3/3052 , H04B1/109 , H04W52/0209
摘要： A method and apparatus are disclosed for a configurable mixer capable of operating in a linear, a legacy, and a low-power mode. In the linear mode, the configurable mixer is configured to operate as a double-balanced mixer to multiply a first differential signal by a second differential signal. In the legacy mode, the configurable mixer is configured to as a double-balanced mixer to multiply a differential signal by a single-ended signal. In the low-power mode, the configurable mixer is configured to operate as a single-balanced mixer to multiply a differential signal by a single-ended signal. The operating mode of the configurable mixer may be based, at least in part, on a mode control signal. In some embodiments, the configurable mixer may be included in an analog front end of a wireless communication device.
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公开(公告)号：US20170323677A1
公开(公告)日：2017-11-09
申请号：US15522344
申请日：2014-10-28
发明人： Ning Ge , John Paul Strachan , Jianhua Yang , Miao Hu
摘要： A method of obtaining a dot product includes applying a programming signal to a number of capacitive memory devices coupled at a number of junctions formed between a number of row lines and a number of column lines. The programming signal defines a number of values within a matrix. The method further includes applying a vector signal. The vector signal defines a number of vector values to be applied to the capacitive memory devices.
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公开(公告)号：US09748935B2
公开(公告)日：2017-08-29
申请号：US15166847
申请日：2016-05-27
发明人： Taesung Kim , Seunguk Yang , Youngbae Park
摘要： Examples of a signal calculator include a voltage multiplier and a time divider. The voltage multiplier copies time information corresponding to a first voltage and generates a third voltage using a second current corresponding to a second voltage during a first period corresponding to the copied time information. The time divider generates an output according to a result of comparing a voltage generated by a first current on the basis of a voltage corresponding to a first time with a second voltage corresponding to a second time.
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公开(公告)号：US09553568B2
公开(公告)日：2017-01-24
申请号：US14925344
申请日：2015-10-28
CPC分类号： H03K5/00006 , G06G7/16 , H03B19/10 , H03B19/14
摘要： A frequency multiplier includes an input terminal, an output terminal, a first transistor having a first gate to which a radiofrequency signal is input from the input terminal, a first drain from which an output signal is issued to the output terminal, and a first source, a second transistor having a second gate, a second source to which the radiofrequency signal is input from the input terminal, and a second drain from which an output signal is issued to the output terminal, and a stabilizing resistor which is a resistor connected to the second gate, wherein no resistor exists on the path for the radiofrequency signal, and wherein the stabilizing resistor suppresses a reflex gain produced by the second transistor.
摘要翻译： 倍频器包括输入端子，输出端子，具有从输入端子输入射频信号的第一栅极的第一晶体管，向输出端子发出输出信号的第一漏极，以及第一源极 ，具有第二栅极的第二晶体管，从输入端子输入射频信号的第二源极和向输出端子发出输出信号的第二漏极，以及稳定电阻器，其是连接到 所述第二栅极，其中在所述射频信号的路径上不存在电阻器，并且其中所述稳定电阻器抑制由所述第二晶体管产生的反射增益。
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公开(公告)号：US09490774B2
公开(公告)日：2016-11-08
申请号：US14619940
申请日：2015-02-11
申请人： ESS Technology, Inc.
发明人： A. Martin Mallinson
摘要： Channel select filter circuits are described. One circuit implements a multiplying element and digital-to-analog converter as a differential current mode device. Another circuit implementing a multiplying element and digital-to-analog converter with weighted addition, deferred after multiplication of the digital-to-analog converter and multiplier combination. In one such circuit, substantially equal current source magnitudes are in different columns of the circuit. Another such circuit, with substantially equal current source magnitudes, uses non-radix2. Another such circuit, with substantially equal current source magnitudes, has partial segmentation. Another circuit implements a multiplying element and digital-to-analog converter, with partial segmentation, scrambling bit allocation for elements. One such circuit scrambles bit allocation on equally weighted segments, as described herein. Another circuit implements a multiplying element and digital-to-analog converter with selective enablement of duplicate current source devices. Another circuit implements a multiplying element and digital-to-analog converter with variable effective length of the digital-to-analog converter. In one such circuit one or more current sources of a multiplier element are deselected to remove a noise contribution of the multiplier element, as described herein. A complex filter circuit includes a pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a common resistor network to perform weighted addition. One such circuit further includes a second pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a second common resistor network to perform weighted addition.
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公开(公告)号：US20160117527A1
公开(公告)日：2016-04-28
申请号：US14526474
申请日：2014-10-28
IPC分类号： G06G7/16
CPC分类号： G06G7/16
摘要： The compact CMOS current-mode analog multifunction circuit is based on an implementation using MOSFETs operating in a sub-threshold region and forming two overlapping translinear loops capable of performing multiplication, division, controllable gain current amplifier, current mode differential amplifier, and differential-input single-output current amplifier.
摘要翻译： 紧凑型CMOS电流模式模拟多功能电路基于使用在亚阈值区域中操作的MOSFET的实现，并形成能够执行乘法，分频，可控增益电流放大器，电流模式差分放大器和差分输入的两个重叠的跨线性回路 单输出电流放大器。
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28.发明授权Digital correlator / FIR filter with tunable bit time using analog summation 有权具有可调位时间的数字相关器/ FIR滤波器，使用模拟求和公开(公告)号：US09053349B1
公开(公告)日：2015-06-09
申请号：US14273245
申请日：2014-05-08
发明人： Randall White , Brian N. Limketkai
CPC分类号： G06G7/14
摘要： A digital correlator including an input, a plurality of serially connected delay elements, wherein a first delay element of the plurality of serially connected delay elements is coupled to the input, a plurality of current elements, wherein each respective current element of the plurality of current elements is coupled to a respective delay element, and each current element has a current, and a summer for summing the currents of the plurality of current elements, the summer having an output for the digital correlator.
摘要翻译： 一种数字相关器，包括输入，多个串行连接的延迟元件，其中多个串联的延迟元件的第一延迟元件耦合到输入端，多个电流元件，其中多个电流中的每个相应的电流元件 元件被耦合到相应的延迟元件，并且每个电流元件具有电流以及用于对多个电流元件的电流求和的加法器，该加法器具有数字相关器的输出。
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公开(公告)号：US08694573B2
公开(公告)日：2014-04-08
申请号：US12647255
申请日：2009-12-24
CPC分类号： G06F7/535 , G06F2207/5356
摘要： A method for determining a quotient value from a dividend value and a divisor value in a digital processing circuit is provided. The method includes computing a reciprocal value of the divisor value and multiplying the reciprocal value by the dividend value to obtain a reciprocal product, the reciprocal product having an integer part. The method also includes computing an intermediate remainder value by computing a product of the integer part and the divisor value, and subtracting the resulting product from the dividend value and determining the quotient value based upon the intermediate remainder value.
摘要翻译： 提供一种用于从数字处理电路中的除数值和除数值确定商值的方法。 该方法包括计算除数值的倒数值，并将倒数值乘以除数值以获得互逆乘积，该倒数乘积具有整数部分。 该方法还包括通过计算整数部分和除数值的乘积来计算中间余数值，并从分红值中减去所得到的乘积，并基于中间余数值确定商值。
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公开(公告)号：US20130176067A1
公开(公告)日：2013-07-11
申请号：US13783589
申请日：2013-03-04
申请人： ViaSat, Inc.
发明人： Kenneth V. Buer
IPC分类号： G06G7/16
CPC分类号： G06G7/16 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D2200/0088
摘要： A MMIC (microwave monolithic integrated circuit) based FET mixer and method for the same is provided. In particular, adjacent transistors, such as FETs (field effect transistors) share terminals reducing physical layout separation and interconnections. A smaller die size is realized with the improved system geometry herein provided.
摘要翻译： 提供了一种基于MMIC（微波单片集成电路）的FET混频器及其方法。 特别地，诸如FET（场效应晶体管）的相邻晶体管共享终端，从而减少物理布局分离和互连。 使用本文提供的改进的系统几何形状实现较小的模具尺寸。
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