公开(公告)号：US10061870B2

公开(公告)日：2018-08-28

申请号：US14217854

申请日：2014-03-18

Applicant: Palo Alto Research Center Incorporated

Inventor： Saigopal Nelaturi ,  Walter Kim ,  Arvind Rangarajan ,  Tolga Kurtoglu

IPC: G06F17/50 ,  G06T19/00 ,  B33Y50/00

CPC classification number: G06F17/50 ,  B33Y50/00 ,  G06F17/5086 ,  G06F2217/12 ,  G06T19/00 ,  G06T2219/008 ,  Y02P90/265

Abstract: A system and a method automate metrology, measurement, and model correction of a three dimensional (3D) model for 3D printability. Slices of the 3D model are received or generated. The slices represent 2D solids of the 3D model to be printed in corresponding print layers. Medial axis transforms of the slices are calculated. The medial axis transforms represent the slices in terms of corresponding medial axes. A local feature size at any point along a boundary of the slices is determined as the shortest distance from the point to a corresponding medial axis.

公开(公告)号：US10057138B1

公开(公告)日：2018-08-21

申请号：US14460729

申请日：2014-08-15

Applicant: VCE Company, LLC

Inventor： Timothy Allen Cox

IPC: G06F17/50 ,  H04L12/24 ,  G06F3/0482 ,  G06F3/0484

CPC classification number: G06F3/04842 ,  G06F17/5004 ,  G06F2217/12

Abstract: A system, method, apparatus, and computer program product for validating a user modification to an elevation plan for a computing system are disclosed. A method may include causing display of a user interface including a representation of at least a portion of the elevation plan. The user interface may be configured to enable user modification of the elevation plan. The method may further include receiving an indication of a mount position for a component. The method may additionally include validating that the component is mountable in the mount position. The method may also include updating the elevation plan to include the component in the mount position in response to validation that the component is mountable in the mount position.

公开(公告)号：US10056304B2

公开(公告)日：2018-08-21

申请号：US15599311

申请日：2017-05-18

Applicant: DECA Technologies Inc.

Inventor： Craig Bishop ,  Vaibhav Joga Singh Bora ,  Christopher M. Scanlan ,  Timothy L. Olson

IPC: G06K9/00 ,  H01L21/66 ,  H01L23/00 ,  H01L21/78 ,  H01L23/544 ,  G06F17/50 ,  G06T7/00 ,  H01L21/768 ,  H01L21/56

CPC classification number: H01L22/12 ,  G06F17/5081 ,  G06F2217/12 ,  G06F2217/40 ,  G06T7/0004 ,  G06T7/001 ,  G06T2207/30148 ,  H01L21/568 ,  H01L21/768 ,  H01L21/78 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L24/73 ,  H01L24/96 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54486 ,  H01L2224/0231 ,  H01L2224/03 ,  H01L2224/04105 ,  H01L2224/0508 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/221 ,  H01L2224/27 ,  H01L2224/29006 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/141 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/18162 ,  H01L2924/3511 ,  Y02P90/265 ,  H01L2224/11

Abstract: An automated optical inspection (AOI) system can comprise aligning a wafer comprising a plurality of unit specific patterns. A plurality of unique reference standards can be created as a plurality of electrical nets by generating with a computer an electrical net for each of the unit specific patterns, each of the plurality of electrical nets comprising a start point and an end point. An image of each of the plurality of unit specific patterns can be captured with a camera. The image can be processed with the computer to provide a plurality of extracted boundaries of contiguous electrically conductive regions. Defects in the plurality of unit specific patterns, if present, can be detected by comparing each of the extracted boundaries of contiguous electrically conductive regions to a corresponding one of the plurality of unique reference standards. An output of known good die can be created.

公开(公告)号：US10055520B2

公开(公告)日：2018-08-21

申请号：US15057853

申请日：2016-03-01

Applicant: Toshiba Memory Corporation

Inventor： Mitsutoshi Nakamura

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5018 ,  G06F17/5045 ,  G06F2217/12 ,  G06F2217/16 ,  Y02P90/265

Abstract: According to an embodiment, a process simulator has a layout processing unit to extract vertex coordinates of a first graphic of a layout of a semiconductor device described in a layout file used for a simulation, an initial mesh generation unit to generate a first initial mesh passing through the vertex coordinates in a plane direction of the layout, and a simulator unit to execute a process simulation of the semiconductor device based on simulation data in which a process flow of the semiconductor device is described, the layout, and the first initial mesh.

公开(公告)号：US10037400B2

公开(公告)日：2018-07-31

申请号：US15611628

申请日：2017-06-01

Applicant: Marvell World Trade Ltd.

Inventor： Runzi Chang ,  Winston Lee ,  Peter Lee

IPC: G11C11/40 ,  G06F17/50 ,  G11C11/412

CPC classification number: G06F17/5077 ,  G06F2217/12 ,  G11C11/412 ,  H01L27/1104 ,  H01L27/1116

Abstract: In some implementations, a method of fabricating an integrated circuit includes obtaining first data for a first chip containing a first version of the integrated circuit, determining that a transistor should be coupled with another transistor, selecting one or more masks for coupling the transistor with the other transistor to adjust the threshold voltage of the transistor, obtaining second data for a second chip containing a second version of the integrated circuit, determining that the second version of the integrated circuit meets one or more requirements, and preparing a final integrated circuit design for production based on the second version of the integrated circuit.

公开(公告)号：US20180210996A1

公开(公告)日：2018-07-26

申请号：US15411599

申请日：2017-01-20

Applicant: Hamilton Sundstrand Corporation

Inventor： Diana Giulietti

IPC: G06F17/50

CPC classification number: G06F17/5086 ,  G06F17/50 ,  G06F2217/12 ,  G06T9/001

Abstract: A computer-implemented method for generating a manufacturing dataset having cloned geometric features for an additive manufacturing process includes identifying, via a processor, a repeating design feature in a first manufacturing dataset that defines a three-dimensional workpiece. The method further includes determining, via the processor, a processing cost or benefit for cloning the repeating design feature, and generating, via the processor, a second dataset having with repeating design feature isolated responsive to the determined processing benefit. The method includes generating, via the processor, a third dataset from the first manufacturing dataset. The third dataset that replaces the repeating design feature with a reference to the second dataset having the repeating design feature.

公开(公告)号：US20180210421A1

公开(公告)日：2018-07-26

申请号：US15867939

申请日：2018-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WOOTAE KIM ,  Hyung-Ock Kim ,  Jaehoon Kim ,  Naya Ha ,  Ki-Ok Kim ,  Eunbyeol Kim ,  Jung Yun Choi ,  Sun Ik Heo

IPC: G05B19/4097 ,  G06F17/50

CPC classification number: G05B19/4097 ,  G05B2219/45031 ,  G06F17/5072 ,  G06F2217/12 ,  Y02P90/265

Abstract: A method of manufacturing an integrated circuit (IC) including instances of standard cells includes arranging a first instance and arranging a second instance adjacent to the first instance. The second instance has a front-end layer pattern corresponding to a context group of the first instance. The context group includes information about front-end layer patterns of instances, the front-end layer patterns causing a same local layout effect (LLE) on the first instance and arranged adjacent to the first instance.

公开(公告)号：US20180210228A1

公开(公告)日：2018-07-26

申请号：US15878587

申请日：2018-01-24

Applicant: Rodenstock GmbH

Inventor： Stephan Trumm ,  Wolfgang Becken ,  Helmut Altheimer ,  Adam Muschielok ,  Yohann Bénard ,  Gregor Esser ,  Anne Seidemann ,  Werner Mueller

IPC: G02C7/02 ,  G06F17/50 ,  G06F17/16 ,  G06F17/11

CPC classification number: G02C7/027 ,  G02C7/028 ,  G06F17/11 ,  G06F17/16 ,  G06F17/50 ,  G06F2217/12 ,  G06F2217/16 ,  Y02P90/265

Abstract: Optimizing and producing a lens by defining an individual eye model, in which a shape of a corneal front surface of a model eye, and a reference aberration at an evaluation surface within the model eye are defined based on individual measurement values for the lens wearer's eye, on standard values, or based on provided individual refraction data; specifying first and second surfaces for the lens to be optimized; determining the path of a main ray through a visual point a surface of the lens into the model eye up to the evaluation surface; evaluating an aberration of a wavefront propagating along the main ray and resulting from a spherical wavefront incident on the first surface of the lens at the evaluation surface in comparison to the reference aberration; and iteratively varying the surface of the lens until the evaluated aberration corresponds to a predetermined target aberration.

公开(公告)号：US20180181684A1

公开(公告)日：2018-06-28

申请号：US15390360

申请日：2016-12-23

Applicant: Movellus Circuits Incorporated

Inventor： Jeffrey Fredenburg ,  Muhammad Faisal ,  David M. Moore ,  Ramin Shirani

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5027 ,  G06F17/5031 ,  G06F2217/06 ,  G06F2217/12

Abstract: A computer-implemented method for manufacturing an integrated circuit (IC) chip includes defining digital block specifications for the IC; and automatically synthesizing and integrating digital blocks with support circuits in accordance with the digital block specifications.

公开(公告)号：US20180173822A1

公开(公告)日：2018-06-21

申请号：US15387373

申请日：2016-12-21

Applicant: ARM Limited

Inventor： Hongwei Zhu ,  Mouli Rajaram Chollangi ,  Hemant Joshi ,  Yew Keong Chong ,  Satinderjit Singh ,  Betsie Jacob ,  Neeraj Dogra ,  Sriram Thyagarajan

IPC: G06F17/50 ,  G06F17/30

CPC classification number: G06F17/5009 ,  G06F17/30289 ,  G06F17/5068 ,  G06F2217/12

Abstract: Various implementations described herein are directed to a computing device. The computing device may include a mapper module that receives a user configuration input of a destination corner for building a destination corner database. The mapper module may include a decision making engine that decides fabrication parameters for building the destination corner database based on the verified user configuration input and memory compiler metadata. The computing device may include a builder module that performs a simulation of the destination corner based on the fabrication parameters, collects simulation results data associated with the simulation, and builds the destination corner database for the destination corner based on the simulation results data and source corner data. The computing device may include a memory compiler that accesses the destination corner database and generates memory instance structures and their electronic digital automation (EDA) views for the destination corner based on the destination corner database.