公开(公告)号：US09229896B2

公开(公告)日：2016-01-05

申请号：US13724886

申请日：2012-12-21

Applicant: Apple Inc.

Inventor： Deniz Balkan ,  Gurjeet S. Saund

IPC: G06F13/36 ,  G06F13/40

CPC classification number: G06F13/4027 ,  G06F13/4059 ,  G06F2213/0038

Abstract: Systems and methods for maintaining an order of read and write transactions for each source through a bridge in a bus fabric. The bridge provides a connection from a first bus to a second bus within the bus fabric. The first bus has a single path for read and write transactions and the second bus has separate paths for read and write transactions. The bridge maintains a pair of counters for each source in a SoC to track the numbers of outstanding read and write transactions. The bridge prevents a read transaction from being forwarded to the second bus if the corresponding write counter is non-zero, and the bridge prevents a write transaction from being forwarded to the second bus if the corresponding read counter is non-zero.

Abstract translation: 用于通过总线结构中的桥梁维护每个源的读取和写入事务顺序的系统和方法。 该桥提供从总线结构中的第一总线到第二总线的连接。 第一个总线具有读取和写入事务的单一路径，第二个总线具有用于读取和写入事务的独立路径。 该桥在SoC中为每个源保留一对计数器，以跟踪未完成的读写事务的数量。 如果相应的写计数器不为零，桥将阻止读事务被转发到第二总线，如果相应的读计数器不为零，桥将阻止写事务被转发到第二总线。

公开(公告)号：US09189442B1

公开(公告)日：2015-11-17

申请号：US14589942

申请日：2015-01-05

Applicant: P4TENTS1, LLC

Inventor： Michael S Smith

IPC: G06F13/00 ,  G06F13/28 ,  G06F13/40 ,  G06F12/02 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F3/0613 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F3/0689 ,  G06F9/44557 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0824 ,  G06F13/1657 ,  G06F13/4059 ,  G06F13/4234 ,  G06F17/505 ,  G06F17/5072 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C7/1072 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: An apparatus and associated method/processing unit are provided for utilizing a memory subsystem including NAND flash memory and dynamic random access memory. Further included is a first circuit for receiving DDR signals and converting the DDR signals to SATA signals. The first circuit includes embedded dynamic random access memory. Also provided is a second circuit for receiving the SATA signals and converting the SATA signals to NAND flash signals. The second circuit is communicatively coupled to the first circuit via a first memory bus associated with a SATA protocol, the NAND flash memory via a second memory bus associated with a NAND flash protocol, and the dynamic random access memory. In operation, data is fetched using a time between an execution of a plurality of threads.

公开(公告)号：US20150248256A1

公开(公告)日：2015-09-03

申请号：US14424283

申请日：2013-09-12

Applicant: THOMSON LICENSING

Inventor： Brian Duane Clevengen

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0608 ,  G06F3/067 ,  G06F9/546 ,  G06F13/1642 ,  G06F13/4059 ,  H04L12/40143 ,  H04L67/2842

Abstract: A method and system are provided for processing a reply message out of order from a first-in-first-out (FIFO) storage, and processing other messages in an order as received in the FIFO storage. The system provides a second FIFO storage for storing any messages that have been retrieved from the first FIFO while searching for the reply message.

Abstract translation: 提供了一种方法和系统，用于处理来自先入先出（FIFO）存储器的顺序的应答消息，并且以FIFO存储器中接收的顺序处理其他消息。 该系统提供第二FIFO存储器，用于存储在搜索回复消息时从第一FIFO检索到的任何消息。

公开(公告)号：US09092581B2

公开(公告)日：2015-07-28

申请号：US13648139

申请日：2012-10-09

Applicant: Intel Corporation

Inventor： Daniel G. Borkowski ,  Krishnakanth V. Sistla

IPC: G06F9/54 ,  G06F13/40

CPC classification number: G06F9/546 ,  G06F9/544 ,  G06F9/545 ,  G06F13/4059

Abstract: A message channel optimization method and system enables multi-flow access to the message channel infrastructure within a CPU of a processor-based system. A user (pcode) employs a virtual channel to submit message channel transactions, with the message channel driver processing the transaction “behind the scenes”. The message channel driver thus allows the user to continue processing without having to block other transactions from being processed. Each transaction will be processed, either immediately or at some future time, by the message channel driver. The message channel optimization method and system are useful for tasks involving message channel transactions as well as non-message channel transactions.

Abstract translation: 消息信道优化方法和系统使得能够对基于处理器的系统的CPU内的消息信道基础设施进行多流访问。 用户（pcode）使用虚拟通道提交消息通道事务，消息通道驱动程序处理事务“幕后”。 因此，消息通道驱动器允许用户继续处理，而不必阻止其他事务被处理。 消息通道驱动程序将立即或在将来的某个时间处理每个事务。 消息信道优化方法和系统对于涉及消息信道事务以及非消息信道事务的任务是有用的。

公开(公告)号：US20150199294A1

公开(公告)日：2015-07-16

申请号：US14671947

申请日：2015-03-27

Applicant: INTEL CORPORATION

Inventor： Kimberly DAVIS ,  Mark SULLIVAN ,  James MITCHELL ,  Patrick THEMINS

IPC: G06F13/42 ,  G06F13/24

CPC classification number: G06F13/4221 ,  G06F11/0709 ,  G06F11/0757 ,  G06F11/2038 ,  G06F11/2043 ,  G06F13/24 ,  G06F13/4059

Abstract: A dual host system and method with back to back non-transparent bridges and a proxy packet generating mechanism. The proxy packet generating mechanism enables the hosts to send interrupt generating packets to each other.

Abstract translation: 具有背对背非透明网桥和代理数据包生成机制的双主机系统和方法。 代理分组生成机制使得主机能够相互发送中断生成分组。

公开(公告)号：US09075926B2

公开(公告)日：2015-07-07

申请号：US12021290

申请日：2008-01-28

Applicant: Yaron Elboim

Inventor： Yaron Elboim

IPC: G06F13/40

CPC classification number: G06F13/4059 ,  G06F13/4045 ,  G06F2213/0026

Abstract: A distributed interconnect bus apparatus for connecting peripheral devices. The apparatus can be utilized to wirelessly connect peripheral devices or to allow the connectivity of such devices over a network. The apparatus includes a first bridge coupled to a root component of an interconnect bus; and a second bridge coupled to an endpoint component of an interconnect bus. The apparatus may further include an acknowledgment (ACK) termination for generating at least an ACK signal; and a flow control mechanism including at least one receiver buffer for temporarily saving data packets of multiple different transactions.

Abstract translation: 一种用于连接外围设备的分布式互连总线设备。 该装置可以用于无线地连接外围设备或允许这样的设备通过网络的连接。 该装置包括耦合到互连总线的根部分的第一桥; 以及耦合到互连总线的端点组件的第二桥。 所述设备还可以包括用于生成至少ACK信号的确认（ACK）终止; 以及包括至少一个用于临时保存多个不同事务的数据分组的接收缓冲器的流控制机构。

公开(公告)号：US20150154138A1

公开(公告)日：2015-06-04

申请号：US14096204

申请日：2013-12-04

Applicant: LSI CORPORATION

Inventor： Shankar More ,  Mandar Joshi ,  Vidyadhar Pinglikar

IPC: G06F13/40

CPC classification number: G06F13/4059 ,  G06F13/385 ,  G06F13/404

Abstract: Methods and structure for emulating wide ports at an expander are provided. An exemplary system includes a Serial Attached Small Computer System Interface (SAS) expander. The expander includes a plurality of physical links, and a controller. The controller is able to identify a physical link coupled with a device, to generate a plurality of virtual physical links that are configured as a virtual wide port coupled with the device, and to present the virtual wide port at the expander in place of the physical link.

Abstract translation: 提供了在扩展器上模拟宽端口的方法和结构。 示例性系统包括串行连接小型计算机系统接口（SAS）扩展器。 扩展器包括多个物理链路和控制器。 控制器能够识别与设备耦合的物理链路，以产生被配置为与设备耦合的虚拟宽端口的多个虚拟物理链路，并且在扩展器处呈现虚拟宽端口以代替物理 链接。

公开(公告)号：US09049125B2

公开(公告)日：2015-06-02

申请号：US13729953

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  David Harriman ,  Blaise Fanning ,  David Lee

IPC: G06F15/16 ,  H04L12/801 ,  G06F13/12 ,  G06F13/38 ,  G06F13/42 ,  G06F13/40

CPC classification number: H04L47/10 ,  G06F5/06 ,  G06F13/124 ,  G06F13/385 ,  G06F13/4059 ,  G06F13/42 ,  G06F13/4221 ,  G06F13/4252 ,  G06F13/4265 ,  G06F13/4269 ,  G06F13/4282 ,  H04L47/30

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

公开(公告)号：US20140310487A1

公开(公告)日：2014-10-16

申请号：US14036508

申请日：2013-09-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： BENJIMAN L. GOODMAN ,  HARRISON M. McCREARY ,  ERIC E. RETTER ,  STEVEN L. ROBERTS ,  JEFFREY A. STUECHELI

IPC: G06F12/12

CPC classification number: G06F12/121 ,  G06F12/0831 ,  G06F12/123 ,  G06F13/4059 ,  G06F2213/0038

Abstract: A unified request queue includes multiple entries for servicing multiple types of requests. Each of the entries of the unified request queue is generally allocable to requests of any of the multiple request types. A number of entries in the unified request queue is reserved for a first request type among the multiple types of requests. The number of entries reserved for the first request type is dynamically varied based on a number of requests of the first request type rejected by the unified request queue due to allocation of entries in the unified request queue to other requests.

Abstract translation: 一个统一的请求队列包括多个条目，用于服务多种类型的请求。 统一请求队列的每个条目通常可分配给多个请求类型中的任何一个的请求。 在多种类型的请求中，统一请求队列中的一些条目被保留用于第一请求类型。 基于由统一请求队列拒绝的第一请求类型的请求数量，由于将统一请求队列中的条目分配给其他请求，为第一请求类型保留的条目数量是动态变化的。

公开(公告)号：US08819306B2

公开(公告)日：2014-08-26

申请号：US13729673

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  David Harriman ,  Blaise Fanning ,  David Lee

IPC: G06F13/00

CPC classification number: H04L47/10 ,  G06F5/06 ,  G06F13/124 ,  G06F13/385 ,  G06F13/4059 ,  G06F13/42 ,  G06F13/4221 ,  G06F13/4252 ,  G06F13/4265 ,  G06F13/4269 ,  G06F13/4282 ,  H04L47/30

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

Abstract translation: 提出了一种增强的通用输入/输出通信架构，协议和相关方法。