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公开(公告)号：US11841810B2
公开(公告)日：2023-12-12
申请号：US17244370
申请日：2021-04-29
IPC分类号： G06F13/20 , G06F13/40 , H03K17/687 , G06F13/42
CPC分类号： G06F13/20 , G06F13/4086 , H03K17/6871 , G06F13/4282 , G06F2213/0016
摘要： A communication interface buffer comprises: a data bus connection adapted to be coupled to a bus interface contact; and a ground. The communication interface buffer also comprises an output transistor with a first current terminal, a second current terminal and a control terminal, the first current terminal coupled to the data bus connection, the second current terminal coupled to ground, and the control terminal adapted to receive a drive signal. The communication interface buffer also comprises a control circuit coupled to the control terminal of the output transistor, wherein the control circuit is configured to: turn off the output transistor during a first interval that starts when the data bus connection is coupled to the bus interface contact; and turn on the output transistor after the first interval is complete.
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公开(公告)号：US20230385107A1
公开(公告)日：2023-11-30
申请号：US18449036
申请日：2023-08-14
IPC分类号： G06F9/48 , G06F16/9035 , G06F9/52 , G06F9/50 , G06F1/06 , G06F13/20 , G06F9/448 , G06F11/10 , H04L1/00 , G06F13/28 , G06F13/40
CPC分类号： G06F9/4881 , G06F2209/503 , G06F9/52 , G06F9/5038 , G06F1/06 , G06F9/5016 , G06F9/5011 , G06F13/20 , G06F9/448 , G06F11/1004 , H04L1/0041 , G06F13/28 , G06F13/4068 , G06F2209/5012 , G06F16/9035
摘要： A computing resource allocation method comprises beginning a first performance of a first task; determining, using a task manager circuit during the first performance of the first task, that a first operation from among the first plurality of operations requires a resource, wherein the resource is external to the processor; determining, using a spinlock circuit, that the resource is unavailable for use; pausing, under control of the task manager, the first performance of the first task at the processor; beginning, using the processor, a second performance of a second task, the second task comprising a second plurality of operations; receiving, at the task manager, a notice from the spinlock that the resource is currently available for use by the processor; and resuming, under control of the task manager, the first performance of the first task at the processor starting with the first operation from among the first plurality of operations.
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公开(公告)号：US11822823B2
公开(公告)日：2023-11-21
申请号：US17889134
申请日：2022-08-16
申请人： SK hynix Inc.
发明人： Choung Ki Song
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0679 , G06F7/50 , G06F7/52 , G06N3/08 , G06F13/20
摘要： A processing-in-memory (PIM) system includes a PIM device and a PIM controller. The PIM device includes a first storage region, a second storage region, and a multiplication/accumulation (MAC) operator configured to receive first data and second data from the first and second storage regions, respectively, to perform a MAC arithmetic operation. The PIM controller controls a memory mode and a MAC mode of the PIM device. The PIM controller is configured to generate and transmit a memory command to the PIM device in the memory mode. In addition, the PIM controller is configured to generate and transmit first to fifth MAC commands to the PIM device in the MAC mode.
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公开(公告)号：US20230367726A1
公开(公告)日：2023-11-16
申请号：US17851357
申请日：2022-06-28
申请人： Vmware, Inc.
发明人： Ran Peng , Yang Bai , Wenchao Cui , Yu Zhao , Zhihao Yao
CPC分类号： G06F13/20 , G06F13/24 , G06F2213/40 , G06F2213/24
摘要： Example computer-implemented methods, media, and systems for processing input/output (I/O) commands using block size aware polling are disclosed. One example method includes creating multiple polling queues and multiple interrupt queues in a transport drivers layer of a storage stack. A first I/O command is received from a core layer of the storage stack and by the transport drivers layer. A ratio of a total number of multiple small block size commands in the transport drivers layer to a total number of multiple outstanding I/O commands in the transport drivers layer is determined to be larger than a predetermined first threshold. In response to determining that the ratio is larger than the predetermined first threshold, the polling mode is applied to the first I/O command through the submission of the first I/O command to a first polling queue in the multiple polling queues.
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公开(公告)号：US11816048B2
公开(公告)日：2023-11-14
申请号：US17953874
申请日：2022-09-27
发明人： Kiushan Pirzadeh
CPC分类号： G06F13/20 , H04L67/02 , G06F2213/0002
摘要： Enhanced techniques for communicating with an integrated circuit chip card are disclosed. An integrated circuit chip card may include a processor, a memory storing a plurality applications executable by the processor, an input/output (I/O) interface, and a network interface coupled to the (I/O) interface. The network interface may implement a plurality of logical ports, and the network interface can be configurable to select between multiple communication protocols to communicate with an external device in a socket communication mode. The network interface can be configured to establish a plurality of communication channels between the external device the integrated circuit chip card using the plurality of logical ports, and each of the communication channels may support communication with one of the plurality of applications.
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公开(公告)号：US11809353B2
公开(公告)日：2023-11-07
申请号：US15476936
申请日：2017-03-31
申请人： INTEL CORPORATION
发明人： Kevan A. Lillie , Shlomi Lalush , Yaakov Dalsace , Adee Ofir Ran , Assaf Benhamou , David Golodni , Itay Tamir , Amir Laufer
IPC分类号： G06F13/20 , G06F13/38 , G06F13/16 , G06F9/4401 , G06F30/18
CPC分类号： G06F13/382 , G06F9/4411 , G06F13/16 , G06F13/20 , G06F30/18 , G06F2213/0024 , G06F2213/0026
摘要： Techniques and apparatus to provide for interactions between system components are described. In one embodiment, an apparatus to provide a component interface, the apparatus comprising at least one memory, a first component comprising at least one register, logic, at least a portion of comprised in hardware, the logic to define at least one interface field stored in the at least one register, generate an interface with a second component based on the at least one interface field, and receive interface information from the second component via the interface, the interface information comprising at least one value for the at least one interface field.
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公开(公告)号：US11809346B2
公开(公告)日：2023-11-07
申请号：US16947937
申请日：2020-08-25
申请人： Atmel Corporation
发明人： Guillaume Pean , Vincent Debout , Marc Maunier
CPC分类号： G06F13/20 , G06F13/102 , G06F13/4068
摘要： In an embodiment, a system comprises: a first bus; a second bus; a first peripheral coupled to the first bus and the second bus, the first peripheral configured to receive a command from the first bus and to generate data in response to the first command; and a second peripheral coupled to the first bus and the second bus, the second peripheral configured to initiate transfer of the generated data from the first peripheral to the second peripheral over the second bus such that access to the generated data through the first bus is prevented.
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公开(公告)号：US20230350823A1
公开(公告)日：2023-11-02
申请号：US17731097
申请日：2022-04-27
申请人： Dell Products L.P.
IPC分类号： G06F13/20
CPC分类号： G06F13/20 , G06F2213/0016 , G06F2213/0026
摘要： An information handling system may include a management controller and a chassis having mounted therein at least one add-in card. The management controller may be configured to: retrieve connection information from the add-in card, the connection information indicating a physical location of the add-in card within the chassis; compare the connection information with expected connection information associated with the information handling system; determine that the physical location of the add-in card within the chassis is in conflict with a restriction associated with the add-in card; and transmit an error message based on the determining.
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公开(公告)号：US11791934B2
公开(公告)日：2023-10-17
申请号：US16092240
申请日：2017-05-02
CPC分类号： H04L1/0061 , G06F1/10 , G06F11/1004 , G06F13/20 , G06F13/4291 , H04L1/0041 , G06F11/1032 , G06F13/4282 , G06F2213/0016 , H04L1/08 , H04L7/041
摘要： Provided is a communication device, including: a transmission and reception unit that transmits and receives a signal with an other communication device; an error detection unit that detects an occurrence of an error by having the transmission and reception unit receive a preamble specifying a type of data to be transmitted next, and comparing a bit sequence of a signal received following the preamble to a bit sequence that should be transmitted for the type specified for transmission by the preamble; and a conflict avoidance unit that, if the occurrence of an error is detected by the error detection unit, instructs the transmission and reception unit to transmit a clock corresponding to a certain number of bits following the preamble, and then transmit an abort signal giving an instruction to terminate communication partway through.
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30.发明授权公开(公告)号：US11789662B2
公开(公告)日：2023-10-17
申请号：US17853741
申请日：2022-06-29
申请人： Rambus Inc.
IPC分类号： G06F3/06 , H03M13/27 , H03M13/05 , G06F11/10 , G06F12/02 , G06F12/06 , G06F13/20 , H04L9/06 , G06F9/4401 , G06F13/42 , G06F13/40
CPC分类号： G06F3/0659 , G06F3/064 , G06F3/0611 , G06F3/0619 , G06F3/0673 , G06F9/4406 , G06F11/1016 , G06F11/1076 , G06F12/0246 , G06F12/0607 , G06F13/20 , G06F13/404 , G06F13/4221 , G06F13/4234 , G06F13/4282 , H03M13/05 , H03M13/27 , H04L9/0662 , G06F2212/1008 , G06F2212/1032 , G06F2212/7201 , G06F2212/7208
摘要： A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.
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