公开(公告)号：US10776294B2

公开(公告)日：2020-09-15

申请号：US14942713

申请日：2015-11-16

Applicant: Atmel Corporation

Inventor： Guillaume Pean ,  Vincent Debout ,  Marc Maunier

IPC: G06F13/20 ,  G06F13/10 ,  G06F13/40

Abstract: In an embodiment, a system comprises: a first bus; a second bus; a first peripheral coupled to the first bus and the second bus, the first peripheral configured to receive a command from the first bus and to generate data in response to the first command; and a second peripheral coupled to the first bus and the second bus, the second peripheral configured to initiate transfer of the generated data from the first peripheral to the second peripheral over the second bus such that access to the generated data through the first bus is prevented.

公开(公告)号：US09626310B2

公开(公告)日：2017-04-18

申请号：US14835418

申请日：2015-08-25

Applicant: Atmel Corporation

Inventor： Guillaume Pean ,  Renaud Tiennot ,  Vincent Debout

IPC: G06F13/16 ,  G06F13/20 ,  G06F13/40

CPC classification number: G06F13/1668 ,  G06F13/20 ,  G06F13/4027 ,  G06F13/4068

Abstract: A microcontroller system is disclosed that includes an access stealing monitor coupled to a bus that is configured to receive a first access request from the bus for a first peripheral, duplicate the first access request, transform the first access request to a second access request on a second peripheral, and transfer the second access request to the bus. In another embodiment, a first peripheral coupled to the bus is configured to receive a first access request from the bus for the first peripheral, duplicate the first access request and transform the first access request to a second access request. A second peripheral coupled to the bus and to the first peripheral is configured to receive the second access request and to respond to the second access request. Methods of access stealing in a microcontroller system are also disclosed.

公开(公告)号：US20200379931A1

公开(公告)日：2020-12-03

申请号：US16947937

申请日：2020-08-25

Applicant: Atmel Corporation

Inventor： Guillaume Pean ,  Vincent Debout ,  Marc Maunier

IPC: G06F13/20 ,  G06F13/10 ,  G06F13/40

Abstract: In an embodiment, a system comprises: a first bus; a second bus; a first peripheral coupled to the first bus and the second bus, the first peripheral configured to receive a command from the first bus and to generate data in response to the first command; and a second peripheral coupled to the first bus and the second bus, the second peripheral configured to initiate transfer of the generated data from the first peripheral to the second peripheral over the second bus such that access to the generated data through the first bus is prevented.

公开(公告)号：US12135658B2

公开(公告)日：2024-11-05

申请号：US17644130

申请日：2021-12-14

Applicant: Atmel Corporation

Inventor： Franck Lunadier ,  Vincent Debout

IPC: G06F13/16 ,  G06F13/14 ,  G06F13/36 ,  G06F13/364 ,  G06F13/42

Abstract: A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.

公开(公告)号：US09910812B2

公开(公告)日：2018-03-06

申请号：US14505003

申请日：2014-10-02

Applicant: Atmel Corporation

Inventor： Guillaume Pean ,  Vincent Debout ,  Patrice Vilchez

IPC: G06F13/00 ,  G06F13/42 ,  G06F9/46 ,  G06F13/40

CPC classification number: G06F13/4208 ,  G06F9/466 ,  G06F13/4022

Abstract: Initiating data transactions on a system bus is disclosed. In some implementations, a controller receives first information from a first peripheral requesting a first data transaction. The first information is received over a first communication link between the controller and the first peripheral. The controller receives second information from a second peripheral requesting a second data transaction. The second information received over a second communication link between the controller and the second peripheral. The controller determines first and second ranks for the first and second data transactions, respectively, based on the first and second information, and initiates based on the first and second ranks, the first and second data transactions on a system bus.

公开(公告)号：US20170004097A1

公开(公告)日：2017-01-05

申请号：US15265057

申请日：2016-09-14

Applicant: Atmel Corporation

Inventor： Franck Lunadier ,  Vincent Debout

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/364

CPC classification number: G06F13/1642 ,  G06F13/14 ,  G06F13/36 ,  G06F13/364 ,  G06F13/4282

Abstract: A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.

Abstract translation: 公开了一种总线架构，其提供在使用总线通信的模块上的事务队列重新分配。 模块可以通过数字电子电路（例如，硬件或软件或两者的组合）来实现事务请求队列。 通过组合使用事务请求重播机制的乱序系统总线协议，可以避免影响常规系统的一些总线堵塞问题。 模块可以从交易请求队列中排除较不紧急的事务，以便插入更紧急事务的空间。 主事件模块可以在事务处于待处理状态时动态更新事务的服务质量（QoS）值。

公开(公告)号：US20160098375A1

公开(公告)日：2016-04-07

申请号：US14505003

申请日：2014-10-02

Applicant: Atmel Corporation

Inventor： Guillaume Pean ,  Vincent Debout ,  Patrice Vilchez

IPC: G06F13/42 ,  G06F13/40 ,  G06F9/46

CPC classification number: G06F13/4208 ,  G06F9/466 ,  G06F13/4022

Abstract: Initiating data transactions on a system bus is disclosed. In some implementations, a controller receives first information from a first peripheral requesting a first data transaction. The first information is received over a first communication link between the controller and the first peripheral. The controller receives second information from a second peripheral requesting a second data transaction. The second information received over a second communication link between the controller and the second peripheral. The controller determines first and second ranks for the first and second data transactions, respectively, based on the first and second information, and initiates based on the first and second ranks, the first and second data transactions on a system bus.

Abstract translation: 公开了在系统总线上启动数据事务。 在一些实现中，控制器从第一外设接收请求第一数据事务的第一信息。 第一信息通过控制器和第一外围设备之间的第一通信链路接收。 控制器从第二外设接收请求第二数据事务的第二信息。 通过控制器和第二外围设备之间的第二通信链路接收的第二信息。 控制器基于第一和第二信息分别确定第一和第二数据事务的第一和第二等级，并且基于第一和第二等级，在系统总线上启动第一和第二数据事务。

公开(公告)号：US11809346B2

公开(公告)日：2023-11-07

申请号：US16947937

申请日：2020-08-25

Applicant: Atmel Corporation

Inventor： Guillaume Pean ,  Vincent Debout ,  Marc Maunier

IPC: G06F13/20 ,  G06F13/10 ,  G06F13/40

CPC classification number: G06F13/20 ,  G06F13/102 ,  G06F13/4068

Abstract: In an embodiment, a system comprises: a first bus; a second bus; a first peripheral coupled to the first bus and the second bus, the first peripheral configured to receive a command from the first bus and to generate data in response to the first command; and a second peripheral coupled to the first bus and the second bus, the second peripheral configured to initiate transfer of the generated data from the first peripheral to the second peripheral over the second bus such that access to the generated data through the first bus is prevented.

公开(公告)号：US11256632B2

公开(公告)日：2022-02-22

申请号：US15265057

申请日：2016-09-14

Applicant: Atmel Corporation

Inventor： Franck Lunadier ,  Vincent Debout

IPC: G06F13/16 ,  G06F13/36 ,  G06F13/14 ,  G06F13/364 ,  G06F13/42

Abstract: A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.

公开(公告)号：US20170329574A1

公开(公告)日：2017-11-16

申请号：US15154287

申请日：2016-05-13

Applicant: Atmel Corporation

Inventor： Guilliaume Pean ,  Renaud Tiennot ,  Vincent Debout ,  Vincent Chanel

IPC: G06F5/14 ,  G06F3/06 ,  G06T1/60 ,  G06F13/28

CPC classification number: G06F5/14 ,  G06F13/28 ,  G06F2205/126

Abstract: The disclosure describes a display controller and a method that includes monitoring a fill-level of a first in, first out (FIFO) block in the display controller, generating a regulation signal that depends on the fill-level of the FIFO block, and regulating, based on the regulation signal, access to a system interconnect by a master unit other than the display controller.