公开(公告)号：US09268698B1

公开(公告)日：2016-02-23

申请号：US14680471

申请日：2015-04-07

申请人： Parallels IP Holdings GmbH

发明人： Denis Lunev

IPC分类号： G06F12/10 ,  G06F12/08 ,  G06F3/06

CPC分类号： G06F12/0844 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0668 ,  G06F3/0673 ,  G06F9/45558 ,  G06F9/50 ,  G06F2003/0691 ,  G06F2009/45591 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/6042

摘要： System for working with shared memory includes a plurality of contexts, each having executable processes writing and reading data; a ring buffer in the shared memory for writing and reading data by the contexts; a software primitive manages access attempts by the contexts to the ring buffer. Each context, upon writing to the ring buffer, is allocated an amount of space up to a maximum available at that moment. The software primitive guarantees consistency of the data written to the ring buffer. The software primitive permits simultaneous writing into the buffer by multiple contexts. After finishing writing to the buffer, the context updates a state of the buffer by decrementing the count of the active writers and/or by shifting the permitting pointers for communicating with writers and readers. A context can read from the buffer only data is marked as valid for reading by the context that wrote that data.

公开(公告)号：US09262326B2

公开(公告)日：2016-02-16

申请号：US11565034

申请日：2006-11-30

申请人： Barry Joe Wolford ,  James Edward Sullivan, Jr.

发明人： Barry Joe Wolford ,  James Edward Sullivan, Jr.

IPC分类号： G06F12/08 ,  G06F13/16

CPC分类号： G06F12/0844 ,  G06F13/1647

摘要： A memory system is disclosed. The memory system includes first and second memory devices, and a memory controller configured to selectively enable one of the memory devices, the memory controller having a first line coupled to the first and second memory devices and a second line coupled to the first and second memory devices. The first memory device is configured to provide a notification to the memory controller on the first line and the second memory device is configured to provide a notification to the memory controller on the second line. The first memory device is further configured not to load the first line and the second memory device is further configured not to load the second line when the memory controller is writing to the enabled memory device.

摘要翻译： 公开了一种存储系统。 存储器系统包括第一和第二存储器设备，以及存储器控制器，被配置为选择性地启用存储器设备中的一个，存储器控制器具有耦合到第一和第二存储器设备的第一线路和耦合到第一和第二存储器的第二线路 设备。 第一存储器设备被配置为向第一行上的存储器控​​制器提供通知，并且第二存储器设备被配置为向第二行上的存储器控​​制器提供通知。 第一存储器设备被进一步配置为不加载第一行，并且当存储器控制器正在写入启用的存储器设备时，第二存储器设备被进一步配置为不加载第二行。

公开(公告)号：US20150199272A1

公开(公告)日：2015-07-16

申请号：US14154122

申请日：2014-01-13

申请人： Apple Inc.

发明人： Rajat Goel ,  Mridul Agarwal

IPC分类号： G06F12/08

CPC分类号： G06F12/0815 ,  G06F12/0844 ,  G06F12/0891

摘要： Systems, processors, and methods for efficiently handling concurrent store and load operations within a processor. A processor comprises a load-store unit (LSU) with a banked level-one (L1) data cache. When a store operation is ready to write data to the L1 data cache, the store operation will skip the write to any banks that have a conflict with a concurrent load operation. A partial write of the store operation will be performed to those banks of the L1 data cache that do not have a conflict with a concurrent load operation. For every attempt to write the store operation, a corresponding store mask will be updated to indicate which portions of the store operation were successfully written to the L1 data cache.

摘要翻译： 用于在处理器内有效处理并发存储和加载操作的系统，处理器和方法。 处理器包括具有一级（L1）数据高速缓存的加载存储单元（LSU）。 当存储操作准备好将数据写入L1数据高速缓存时，存储操作将跳过对与并发加载操作冲突的任何存储区的写操作。 将对与数据并行加载操作不冲突的L1数据高速缓存区进行存储操作的部分写入。 对于每次尝试写存储操作时，将更新相应的存储掩码，以指示存储操作的哪些部分已成功写入L1数据高速缓存。

公开(公告)号：US20150039832A1

公开(公告)日：2015-02-05

申请号：US14017766

申请日：2013-09-04

申请人： LSI Corporation

发明人： Vineet Agarwal ,  Ashish Jain ,  Amit Kumar Sharma

IPC分类号： G06F12/08

CPC分类号： G06F12/0844

摘要： The disclosure is directed to a system and method of cache management for a data storage system. According to various embodiments, the cache management system includes a hinting driver and a priority controller. The hinting driver generates pointers based upon data packets intercepted from data transfer requests being processed by a host controller of the data storage system. The priority controller determines whether the data packets are associated with at least a first (high) priority level or a second (normal or low) priority level based upon the pointers generated by the hinting driver. High priority data packets are stored in cache memory regardless of whether they satisfy a threshold heat quotient (i.e. a selected level of data transfer activity).

摘要翻译： 本公开涉及用于数据存储系统的高速缓存管理系统和方法。 根据各种实施例，高速缓存管理系统包括提示驱动器和优先级控制器。 提示驱动器基于由数据存储系统的主机控制器正在处理的数据传送请求截取的数据包生成指针。 优先级控制器基于由提示驱动器生成的指针来确定数据分组是否与至少第一（高）优先级或第二（正常或低）优先级关联。 不管它们是否满足阈值热商（即所选择的数据传输活动级别），高优先级数据分组都被存储在高速缓冲存储器中。

公开(公告)号：US20150012690A1

公开(公告)日：2015-01-08

申请号：US14217436

申请日：2014-03-17

申请人： ROLANDO H. BRUCE ,  ELMER PAULE DELA CRUZ ,  MARK IAN ALCID ARCEDERA

发明人： ROLANDO H. BRUCE ,  ELMER PAULE DELA CRUZ ,  MARK IAN ALCID ARCEDERA

IPC分类号： G06F3/06 ,  G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/0844 ,  G06F12/0868 ,  G06F2212/1016 ,  G06F2212/217 ,  G06F2212/225 ,  G06F2212/313

摘要： A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower. Methods provided here may be extended for systems that have more than two cache levels.

摘要翻译： 描述了具有包括旋转驱动器，闪存装置，SDRAM和SRAM的不同类型的存储装置的混合的混合存储系统。 旋转驱动器用作主存储器，提供每单位存储存储器的最低成本。 闪存用作旋转驱动器的更高级缓存。 提供了用于管理该存储系统的多级缓存的方法，其具有由易失性存储器（SRAM或SDRAM）组成的非常快速的1级缓存以及使用闪存器件阵列的非易失性级别2高速缓存。 它描述了一种在旋转驱动器之间分配数据以使缓存更有效率的方法。 它还描述了将数据从L1高速缓存和L2高速缓存冲刷到旋转驱动器的有效技术，利用并发闪存设备操作，并发旋转驱动操作和最大化旋转驱动器中的顺序访问类型，而不是相对较慢的随机访问。 这里提供的方法可以扩展到具有两个以上缓存级别的系统。

公开(公告)号：US20140365729A1

公开(公告)日：2014-12-11

申请号：US13912809

申请日：2013-06-07

申请人： Advanced Micro Devices, Inc.

发明人： Marius Evers ,  John Kalamatianos ,  Carl D. Dietz ,  Richard E. Klass ,  Ravindra N. Bhargava

IPC分类号： G06F12/08

CPC分类号： G06F12/0855 ,  G06F12/0844 ,  G06F12/0846

摘要： The present application describes embodiments of techniques for picking a data array lookup request for execution in a data array pipeline a variable number of cycles behind a corresponding tag array lookup request that is concurrently executing in a tag array pipeline. Some embodiments of a method for picking the data array lookup request include picking the data array lookup request for execution in a data array pipeline of a cache concurrently with execution of a tag array lookup request in a tag array pipeline of the cache. The data array lookup request is picked for execution in response to resources of the data array pipeline becoming available after picking the tag array lookup request for execution. Some embodiments of the method may be implemented in a cache.

摘要翻译： 本申请描述了用于在数据阵列流水线中选择用于执行数据阵列查找请求的技术的实施例，该数据阵列查找请求在标签阵列管线中同时执行的对应的标签数组查找请求后面的可变数量的循环。 用于选择数据阵列查找请求的方法的一些实施例包括在高速缓存的标签阵列管线中执行标签阵列查找请求的同时，在高速缓存的数据阵列流水线中选择用于执行的数据阵列查找请求。 选择数据数组查找请求以在执行标签数组查找请求之后响应于数据数组流水线变得可用的资源进行执行。 该方法的一些实施例可以在高速缓存中实现。

公开(公告)号：US20140317356A1

公开(公告)日：2014-10-23

申请号：US13864542

申请日：2013-04-17

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Sriram Srinivasan ,  Tarun Nakra

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F12/0844 ,  G06F12/0857 ,  Y02D10/13

摘要： A processor includes a processing unit, a cache memory, and a central request queue. The central request queue is operable to receive a prefetch load request for a cache line to be loaded into the cache memory, receive a demand load request for the cache line from the processing unit, merge the prefetch load request and the demand load request to generate a promoted load request specifying the processing unit as a requestor, receive the cache line associated with the promoted load request, and forward the cache line to the processing unit.

摘要翻译： 处理器包括处理单元，高速缓冲存储器和中央请求队列。 中央请求队列可操作以接收用于要加载到高速缓存存储器中的高速缓存行的预取加载请求，从处理单元接收对高速缓存行的请求加载请求，合并预取加载请求和请求加载请求以生成 指定处理单元作为请求者的升级加载请求，接收与所提升的加载请求相关联的高速缓存行，并将高速缓存行转发到处理单元。

公开(公告)号：US08843690B2

公开(公告)日：2014-09-23

申请号：US13179709

申请日：2011-07-11

申请人： Dmitry Podvalny ,  Alex Shinkar ,  Assaf Rachlevski

发明人： Dmitry Podvalny ,  Alex Shinkar ,  Assaf Rachlevski

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/08 ,  G06F12/0844

摘要： An apparatus having a memory and circuit is disclosed. The memory may (i) assert a first signal in response to detecting a conflict between at least two addresses requesting access to a block at a first time, (ii) generate a second signal in response to a cache miss caused by an address requesting access to the block at a second time and (iii) store a line fetched in response to the cache miss in another block by adjusting the first address by an offset. The second time is generally after the first time. The circuit may (i) generate the offset in response to the assertion of the first signal and (ii) present the offset in a third signal to the memory in response to the assertion of the second signal corresponding to reception of the first address at the second time. The offset is generally associated with the first address.

摘要翻译： 公开了一种具有存储器和电路的装置。 存储器可以（i）响应于检测到在第一时间请求对块的访问的至少两个地址之间的冲突来声明第一信号，（ii）响应于由请求访问的地址引起的高速缓存未命中而产生第二信号 并且（iii）通过将第一地址调整为偏移来存储响应于另一个块中的高速缓存未命中取出的行。 第二次是第一次。 电路可以（i）响应于第一信号的断言产生偏移，并且（ii）响应于对应于在第一信号的第一个地址的接收的第二信号的确认，将第三信号中的偏移呈现给存储器 第二次。 偏移量通常与第一个地址相关联。

公开(公告)号：US08839025B2

公开(公告)日：2014-09-16

申请号：US13250443

申请日：2011-09-30

申请人： Ramaswamy Sivaramakrishnan ,  Ali Vahidsafa ,  Aaron S. Wynn ,  Connie W. Cheung

发明人： Ramaswamy Sivaramakrishnan ,  Ali Vahidsafa ,  Aaron S. Wynn ,  Connie W. Cheung

IPC分类号： G06F11/00 ,  G06F11/16 ,  G06F12/12 ,  G06F9/30 ,  G06F12/08 ,  G06F11/20

CPC分类号： G06F11/0793 ,  G06F9/30 ,  G06F9/30047 ,  G06F11/073 ,  G06F11/1666 ,  G06F11/20 ,  G06F12/0804 ,  G06F12/0844 ,  G06F12/0891 ,  G06F12/126 ,  G06F2212/1008 ,  G06F2212/1032

摘要： The systems and methods described herein may provide a flush-retire instruction for retiring “bad” cache locations (e.g., locations associated with persistent errors) to prevent their allocation for any further accesses, and a flush-unretire instruction for unretiring cache locations previously retired. These instructions may be implemented as hardware instructions of a processor. They may be executable by processes executing in a hyper-privileged state, without the need to quiesce any other processes. The flush-retire instruction may atomically flush a cache line implicated by a detected cache error and set a lock bit to disable subsequent allocation of the corresponding cache location. The flush-unretire instruction may atomically flush an identified cache line (if valid) and clear the lock bit to re-enable subsequent allocation of the cache location. Various bits in the encodings of these instructions may identify the cache location to be retired or unretired in terms of the physical cache structure.

摘要翻译： 本文描述的系统和方法可以提供用于退出“不良”高速缓存位置（例如，与持续错误相关联的位置）的刷新退出指令，以防止其对任何进一步访问的分配，以及用于撤销先前退休的高速缓存位置的刷新指令 。 这些指令可以被实现为处理器的硬件指令。 它们可以由以超级特权状态执行的进程执行，而不需要使任何其他进程停顿。 刷新 - 退出指令可以原子地刷新由检测到的高速缓存错误所牵连的高速缓存行，并设置锁定位以禁用对应的高速缓存位置的后续分配。 flush-unretire指令可以原子地刷新已识别的高速缓存行（如果有效）并清除锁定位以重新启用高速缓存位置的后续分配。 这些指令的编码中的各个比特可以根据物理高速缓存结构来标识要退休或未退出的高速缓存位置。

公开(公告)号：US08832111B2

公开(公告)日：2014-09-09

申请号：US13227393

申请日：2011-09-07

申请人： Venkateshwaran Venkataramani ,  George Cabrera, III ,  Venkatasiva Prasad Chakkabala ,  Mark Marchukov ,  Dmitri Petrov

发明人： Venkateshwaran Venkataramani ,  George Cabrera, III ,  Venkatasiva Prasad Chakkabala ,  Mark Marchukov ,  Dmitri Petrov

IPC分类号： G06F7/00 ,  G06F17/30

CPC分类号： G06F17/3048 ,  G06F12/0844 ,  G06F17/30132 ,  G06F17/3033 ,  G06F17/30377 ,  G06F17/30424 ,  G06F17/30457 ,  G06F17/30554 ,  G06F17/30575 ,  G06F17/30595 ,  G06F17/30876 ,  G06F17/30902 ,  G06F17/30958 ,  G06F2212/463 ,  G06F2212/60 ,  H04L67/2842

摘要： A distributed caching system for storing and serving information modeled as a graph that includes nodes and edges that define associations or relationships between nodes that the edges connect in the graph.

摘要翻译： 分布式缓存系统，用于存储和提供建模为图形的信息，该图形包括定义图中边缘连接的节点之间的关联或关系的节点和边。