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    Multi-Leveled Cache Management in a Hybrid Storage System
    2.
    发明申请
    Multi-Leveled Cache Management in a Hybrid Storage System 有权
    混合存储系统中的多级缓存管理

    公开(公告)号：US20150012690A1

    公开(公告)日：2015-01-08

    申请号：US14217436

    申请日：2014-03-17

    申请人： ROLANDO H. BRUCE ,  ELMER PAULE DELA CRUZ ,  MARK IAN ALCID ARCEDERA

    发明人： ROLANDO H. BRUCE ,  ELMER PAULE DELA CRUZ ,  MARK IAN ALCID ARCEDERA

    IPC分类号： G06F3/06 ,  G06F12/08

    CPC分类号： G06F12/0811 ,  G06F12/0844 ,  G06F12/0868 ,  G06F2212/1016 ,  G06F2212/217 ,  G06F2212/225 ,  G06F2212/313

    摘要： A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower. Methods provided here may be extended for systems that have more than two cache levels.

    摘要翻译： 描述了具有包括旋转驱动器，闪存装置，SDRAM和SRAM的不同类型的存储装置的混合的混合存储系统。 旋转驱动器用作主存储器，提供每单位存储存储器的最低成本。 闪存用作旋转驱动器的更高级缓存。 提供了用于管理该存储系统的多级缓存的方法，其具有由易失性存储器（SRAM或SDRAM）组成的非常快速的1级缓存以及使用闪存器件阵列的非易失性级别2高速缓存。 它描述了一种在旋转驱动器之间分配数据以使缓存更有效率的方法。 它还描述了将数据从L1高速缓存和L2高速缓存冲刷到旋转驱动器的有效技术，利用并发闪存设备操作，并发旋转驱动操作和最大化旋转驱动器中的顺序访问类型，而不是相对较慢的随机访问。 这里提供的方法可以扩展到具有两个以上缓存级别的系统。

    Expandable flash-memory mass-storage using shared buddy lines and intermediate flash-bus between device-specific buffers and flash-intelligent DMA controllers
    4.
    发明授权
    Expandable flash-memory mass-storage using shared buddy lines and intermediate flash-bus between device-specific buffers and flash-intelligent DMA controllers 失效
    使用共享伙伴线和设备特定缓冲区和闪存智能DMA控制器之间的中间闪存总线的可扩展闪存大容量存储

    公开(公告)号：US5822251A

    公开(公告)日：1998-10-13

    申请号：US939601

    申请日：1997-09-29

    申请人： Ricardo H. Bruce ,  Rolando H. Bruce ,  Earl T. Cohen

    发明人： Ricardo H. Bruce ,  Rolando H. Bruce ,  Earl T. Cohen

    IPC分类号： G06F11/10 ,  G06F12/02 ,  G06F13/28 ,  G11C13/00

    CPC分类号： G06F12/0246 ,  G06F11/1068 ,  G06F12/0802 ,  G06F13/28 ,  G06F2212/1036 ,  G06F2212/7211

    摘要： A flash-memory system is expandable. Rather than directly connecting individual flash-memory chips to a controller, flash buffer chips are used. Each flash buffer chip can connect to four banks of flash-memory chips. Chip enables for individual chips in a bank are generated from an address sent to the flash buffer chips. Two flash-specific DMA controllers are provided, each with four DMA state machines for controlling the four banks of flash-memory chips attached to a flash buffer chip. This allows for four-way interleaving. Two flash buses connect the two DMA controllers to flash buffer chips. The flash bus has a narrow byte-wide interface to send command, address, and data bytes from the DMA controller to the flash buffer chips. These command, address, and data bytes are then passed through the flash buffer chip to the flash-memory chips. Two additional command signals on the flash bus are used to select and control the flash buffer chips. Busy signals from all flash-memory chips in a bank are connected together, and the four busy signals from the four banks are time-multiplexed to a single common busy line for the flash bus. The four DMA state machines each monitor one period of the busy line, allowing four flash operations to be monitored at a time, even though only one data transfer can occur across the flash bus.

    摘要翻译： 闪存系统是可扩展的。 使用闪存缓冲芯片，而不是将各个闪存芯片直接连接到控制器。 每个闪存缓冲芯片可以连接到四组闪存芯片。 通过从发送到闪存缓冲器芯片的地址生成存储体中的各个芯片的芯片使能。 提供了两个闪存专用DMA控制器，每个具有四个DMA状态机，用于控制连接到闪存缓冲器芯片的四组闪存芯片。 这允许四路交错。 两个闪存总线将两个DMA控制器连接到闪存缓冲芯片。 闪存总线具有窄字节宽接口，用于从DMA控制器向闪存缓冲区芯片发送命令，地址和数据字节。 然后将这些命令，地址和数据字节通过闪存缓冲器芯片传递到闪存芯片。 闪存总线上的两个附加命令信号用于选择和控制闪存缓冲芯片。 来自银行中所有闪存芯片的忙信号连接在一起，来自四个组的四个忙信号被时分复用到闪存总线的单个公共忙线。 四个DMA状态机每个都监视忙线的一个周期，允许一次监视四个闪存操作，即使在闪存总线上只能发生一次数据传输。

    Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage
    5.
    发明授权
    Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage 失效
    具有双写入计数器的统一重新映射和缓存索引表，用于非易失性闪存RAM大容量存储的磨损均衡

    公开(公告)号：US6000006A

    公开(公告)日：1999-12-07

    申请号：US918203

    申请日：1997-08-25

    申请人： Ricardo H. Bruce ,  Rolando H. Bruce ,  Earl T. Cohen ,  Allan J. Christie

    发明人： Ricardo H. Bruce ,  Rolando H. Bruce ,  Earl T. Cohen ,  Allan J. Christie

    IPC分类号： G06F11/10 ,  G06F12/02 ,  G06F13/28 ,  G06F12/10

    CPC分类号： G06F12/0802 ,  G06F11/1068 ,  G06F12/0246 ,  G06F13/28 ,  G06F2212/1036 ,  G06F2212/7211

    摘要： A flash-memory system provides solid-state mass storage as a replacement to a hard disk. A unified re-map table in a RAM is used to arbitrarily re-map all logical addresses from a host system to physical addresses of flash-memory devices. Each entry in the unified re-map table contains a physical block address (PBA) of the flash memory allocated to the logical address, and a cache valid bit and a cache index. When the cache valid bit is set, the data is read or written to a line in the cache pointed to by the cache index. A separate cache tag RAM is not needed. When the cache valid bit is cleared, the data is read from the flash memory block pointed to by the PBA. Two write count values are stored with the PBA in the table entry. A total-write count indicates a total number of writes to the flash block since manufacture. An incremental-write count indicates the number of writes since the last wear-leveling operation that moved the block. Wear-leveling is performed on a block being written when both total and incremental counts exceed system-wide total and incremental thresholds. The incremental-write count is cleared after a block is wear-leveled, but the total-write count is never cleared. The incremental-write count prevents moving a block again immediately after wear-leveling. The thresholds are adjusted as the system ages to provide even wear.

    摘要翻译： 闪存系统提供固态大容量存储作为硬盘的替代品。 RAM中的统一重新映射表用于将所有逻辑地址从主机系统重新映射到闪存设备的物理地址。 统一重映射表中的每个条目包含分配给逻辑地址的闪速存储器的物理块地址（PBA），高速缓存有效位和高速缓存索引。 当缓存有效位置位时，数据被读取或写入高速缓存索引指向的缓存中的一行。 不需要单独的缓存标签RAM。 当缓存有效位被清除时，从PBA指向的闪存块中读取数据。 两个写入计数值与PBA存储在表项中。 总写入计数表示自制造以来写入闪存块的总数。 增量写入计数表示自上次磨损均衡操作以来移动块的写入次数。 当总计数和增量计数都超过系统范围的总和增量阈值时，对写入的块执行磨损均衡。 增量写入计数在块磨损均匀后清除，但总写入计数不会被清除。 增量写入计数可防止在磨损均衡后立即重新移动块。 当系统老化时，会调整阈值以提供均匀的磨损。

    Parallel erase operations in memory systems
    8.
    发明授权
    Parallel erase operations in memory systems 有权

    公开(公告)号：US06529416B2

    公开(公告)日：2003-03-04

    申请号：US09819423

    申请日：2001-03-27

    申请人： Ricardo H. Bruce ,  Rolando H. Bruce

    发明人： Ricardo H. Bruce ,  Rolando H. Bruce

    IPC分类号： G11C1604

    CPC分类号： G06F12/0804 ,  G06F2212/2022 ,  G11C16/10 ,  G11C16/16

    摘要： An apparatus for and method of memory operation having a memory, a cache containing a plurality of entries with a plurality of the entries to be written to memory, a detector for detecting in the cache the plurality of entries to be written to memory, and a processor for erasing a first portion of the memory to accommodate the plurality of entries to be written to memory and writing to the first portion of the memory the plurality of entries to be written to memory wherein an erase operation is followed by a plurality of sequential write operations.

    Transparent management at host interface of flash-memory overhead-bytes using flash-specific DMA having programmable processor-interrupt of high-level operations
    9.
    发明授权
    Transparent management at host interface of flash-memory overhead-bytes using flash-specific DMA having programmable processor-interrupt of high-level operations 失效
    使用具有高级操作可编程处理器中断的闪存专用DMA的闪存存储器开销字节的主机接口进行透明管理

    公开(公告)号：US5956743A

    公开(公告)日：1999-09-21

    申请号：US939602

    申请日：1997-09-29

    申请人： Ricardo H. Bruce ,  Rolando H. Bruce ,  Earl T. Cohen

    发明人： Ricardo H. Bruce ,  Rolando H. Bruce ,  Earl T. Cohen

    IPC分类号： G06F11/10 ,  G06F12/02 ,  G06F13/28 ,  G06F11/08

    CPC分类号： G06F12/0246 ,  G06F11/1068 ,  G06F12/0802 ,  G06F13/28 ,  G06F2212/1036 ,  G06F2212/7211

    摘要： A flash-memory system adds system-overhead bytes to each page of data stored in flash memory chips. The overhead bytes store system information such as address pointers for bad-block replacement and write counters used for wear-leveling. The overhead bytes also contain an error-correction (ECC) code when stored in the flash-memory chips. A DRAM cache stores the pages of data as enlarged pages with the overhead bytes, even though the enlarged pages are not aligned to a power of 2. When an enlarged page is read out of a flash-memory chip, its ECC code is immediately checked and the ECC code in the overhead bytes is replaced with a syndrome code and stored in the DRAM cache. A local processor for the flash-memory system then reads the syndrome code in the overhead bytes and repairs any error using repair information in the syndrome. The overhead bytes are stripped off when pages are transferred from the DRAM cache to a host. The host can be notified early by an intermediate interrupt after a programmable number of pages have been read. This improves performance since the host does not have to wait for an entire block of pages to be read.

    摘要翻译： 闪存系统将系统开销字节添加到存储在闪存芯片中的每一页数据。 开销字节存储用于坏块替换的地址指针和用于磨损均衡的写入计数器的系统信息。 当存储在闪存芯片中时，开销字节还包含纠错（ECC）代码。 DRAM高速缓存将数据页面作为具有开销字节的扩展页存储，即使放大的页面未对齐于2的功率。当从闪速存储器芯片读出放大的页面时，其ECC代码被立即检查 并且开销字节中的ECC代码被替换为校正码并存储在DRAM高速缓存中。 然后闪存系统的本地处理器读取开销字节中的校验码，并使用校正信息中的修复信息修复任何错误。 当页面从DRAM缓存传输到主机时，开销字节被剥离。 读取可编程页数之后，可以通过中间中断提前通知主机。 这样可以提高性能，因为主机不必等待整个页面的读取。