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1.发明授权Method and apparatus to enable the cooperative signaling of a shared bus interrupt in a multi-rank memory subsystem 有权能够在多级存储器子系统中启用共享总线中断的协同信令的方法和装置公开(公告)号：US09262326B2
公开(公告)日：2016-02-16
申请号：US11565034
申请日：2006-11-30
CPC分类号： G06F12/0844 , G06F13/1647
摘要： A memory system is disclosed. The memory system includes first and second memory devices, and a memory controller configured to selectively enable one of the memory devices, the memory controller having a first line coupled to the first and second memory devices and a second line coupled to the first and second memory devices. The first memory device is configured to provide a notification to the memory controller on the first line and the second memory device is configured to provide a notification to the memory controller on the second line. The first memory device is further configured not to load the first line and the second memory device is further configured not to load the second line when the memory controller is writing to the enabled memory device.
摘要翻译： 公开了一种存储系统。 存储器系统包括第一和第二存储器设备，以及存储器控制器，被配置为选择性地启用存储器设备中的一个，存储器控制器具有耦合到第一和第二存储器设备的第一线路和耦合到第一和第二存储器的第二线路 设备。 第一存储器设备被配置为向第一行上的存储器控制器提供通知，并且第二存储器设备被配置为向第二行上的存储器控制器提供通知。 第一存储器设备被进一步配置为不加载第一行，并且当存储器控制器正在写入启用的存储器设备时，第二存储器设备被进一步配置为不加载第二行。
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公开(公告)号：US07921249B2
公开(公告)日：2011-04-05
申请号：US12561381
申请日：2009-09-17
IPC分类号： G06F13/00
CPC分类号： G06F13/1621 , G06F9/52 , G06F9/522
摘要： The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barriers, to the memory. The processing system also includes a slave device configured to provide the master device access to the memory, the slave device being further configured to produce a signal indicating that an ordering constraint imposed by a memory barrier issued by the master device will be enforced, the signal being produced before the execution of all memory access requests issued by the master device to the memory before the memory barrier.
摘要翻译： 本公开涉及一种弱有序处理系统和在弱有序处理系统中执行存储障碍的方法。 处理系统包括存储器和被配置为向存储器发出存储器访问请求（包括存储器障碍）的主设备。 处理系统还包括被配置为提供主设备对存储器的访问的从设备，从设备还被配置为产生指示由主设备发布的存储器障碍施加的排序约束将被强制的信号，信号 在执行由主设备发出的所有存储器访问请求之前在存储器屏障之前被产生到存储器。
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3.发明授权Efficient execution of memory barrier bus commands with order constrained memory accesses 有权具有订单约束的存储器访问的存储器障碍总线命令的高效执行公开(公告)号：US07917676B2
公开(公告)日：2011-03-29
申请号：US11397287
申请日：2006-04-04
IPC分类号： G06F13/00
CPC分类号： G06F13/1621 , G06F9/52 , G06F9/522
摘要： The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barriers, to the memory. The processing system also includes a slave device configured to provide the master device access to the memory, the slave device being further configured to produce a signal indicating that an ordering constraint imposed by a memory barrier issued by the master device will be enforced, the signal being produced before the execution of all memory access requests issued by the master device to the memory before the memory barrier.
摘要翻译： 本公开涉及一种弱有序处理系统和在弱有序处理系统中执行存储障碍的方法。 处理系统包括存储器和被配置为向存储器发出存储器访问请求（包括存储器障碍）的主设备。 处理系统还包括被配置为提供主设备对存储器的访问的从设备，从设备还被配置为产生指示由主设备发布的存储器障碍施加的排序约束将被强制的信号，信号 在执行由主设备发出的所有存储器访问请求之前在存储器屏障之前被产生到存储器。
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公开(公告)号：US07783817B2
公开(公告)日：2010-08-24
申请号：US11468894
申请日：2006-08-31
IPC分类号： G06F13/36
CPC分类号： G06F13/161
摘要： A weakly-ordered processing system implements an execution synchronization bus transaction, or “memory barrier” bus transaction, to enforce strongly-ordered data transfer bus transactions. A slave device that ensures global observability may “opt out” of the memory barrier protocol. In various embodiments, the opt-out decision may be made dynamically by each slave device asserting a signal, may be set system-wide during a Power-On Self Test (POST) by polling the slave devices and setting corresponding bits in a global observability register, or it may be hardwired by system designers so that only slave devices capable of performing out-of-order data transfer operations participate in the memory barrier protocol.
摘要翻译： 弱有序的处理系统实现执行同步总线事务或“存储障碍”总线事务，以执行强有序的数据传输总线事务。 确保全局可观察性的从设备可以“选择退出”存储器屏障协议。 在各种实施例中，可以通过断言信号的每个从设备动态地进行选择退出决定，可以在上电自检（POST）期间通过轮询从设备并将全局可观察性设置相应位来系统地设置 或者可以由系统设计人员进行硬连线，使得只能执行无序数据传输操作的从设备参与存储器屏障协议。
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公开(公告)号：US20100005208A1
公开(公告)日：2010-01-07
申请号：US12561381
申请日：2009-09-17
IPC分类号： G06F13/00
CPC分类号： G06F13/1621 , G06F9/52 , G06F9/522
摘要： The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barriers, to the memory. The processing system also includes a slave device configured to provide the master device access to the memory, the slave device being further configured to produce a signal indicating that an ordering constraint imposed by a memory barrier issued by the master device will be enforced, the signal being produced before the execution of all memory access requests issued by the master device to the memory before the memory barrier.
摘要翻译： 本公开涉及一种弱有序处理系统和在弱有序处理系统中执行存储障碍的方法。 处理系统包括存储器和被配置为向存储器发出存储器访问请求（包括存储器障碍）的主设备。 处理系统还包括被配置为提供主设备对存储器的访问的从设备，从设备还被配置为产生指示由主设备发布的存储器障碍施加的排序约束将被强制的信号，信号 在执行由主设备发出的所有存储器访问请求之前在存储器屏障之前被产生到存储器。
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6.发明授权Method and apparatus for obtaining memory status information cross-reference to related applications 有权用于获取存储器状态信息的相关应用的交叉引用的方法和装置公开(公告)号：US07620783B2
公开(公告)日：2009-11-17
申请号：US11553588
申请日：2006-10-27
IPC分类号： G06F12/00
CPC分类号： G11C7/1045 , G11C5/04 , G11C7/04 , G11C7/1072 , G11C11/406 , G11C11/40626 , G11C2029/0411 , G11C2211/4061
摘要： In one embodiment taught herein, a memory module selectively uses its write data mask input as a status output on which it provides status signaling to an associated memory controller. The memory module configures its data mask input as a status output at one or more times not conflicting with write operations. Correspondingly, the memory controller configures its write data mask output as a status input at such times, for receipt of status signaling from the memory module. In one embodiment, the memory module maintains a status register related to one or more operating conditions of the module, such as temperature, and signals status information changes to the memory controller by driving the module's data mask input. In response to such signaling, the memory controller initiates a read of the module's status register to obtain updated status information, and takes appropriate action, such as by changing the module's refresh rate.
摘要翻译： 在本文教导的一个实施例中，存储器模块选择性地使用其写入数据掩模输入作为其向其提供状态信号给相关联的存储器控制器的状态输出。 存储器模块将其数据掩码输入配置为一次或多次的状态输出，而不与写入操作冲突。 相应地，存储器控制器将其写入数据掩模输出配置为在这种时间的状态输入，以从存储器模块接收状态信号。 在一个实施例中，存储器模块通过驱动模块的数据掩码输入来维持与模块的一个或多个操作条件相关的状态寄存器，例如温度，以及信号状态信息改变到存储器控制器。 响应于这种信令，存储器控制器启动对模块的状态寄存器的读取以获得更新的状态信息，并且采取适当的动作，例如通过改变模块的刷新率。
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公开(公告)号：US07593279B2
公开(公告)日：2009-09-22
申请号：US11548430
申请日：2006-10-11
IPC分类号： G11C11/00
CPC分类号： G11C11/406 , G11C7/1045 , G11C11/40626
摘要： Status information comprising data not stored in a memory array is efficiently read from a plurality of parallel memory devices sharing an N-bit data bus by configuring each memory device to drive the status information on a different subset M of the N bits, and tri-state the remaining N-M bits. Each memory device is additionally configured to drive zero, one or more data strobes associated with the subset M, and tri-state the remaining data strobes. A memory controller may simultaneously read status information from two or more memory devices in parallel, with each memory device driving a separate subset M of the N-bit bus. Each memory device may serialize the status information, and drive it on the subset M of the bus in burst form. Each memory device may include a configuration register initialized by a memory controller to define its subset M.
摘要翻译： 包含未存储在存储器阵列中的数据的状态信息通过配置每个存储器件来驱动N位的不同子集M上的状态信息，从共享N位数据总线的多个并行存储器件中被有效地读取， 说明剩余的NM位。 每个存储器件还被配置为驱动与子集M相关联的零个，一个或多个数据选通，并且三态化剩余的数据选通。 存储器控制器可以并行地从两个或多个存储器件读取状态信息，每个存储器件驱动N位总线的单独的子集M. 每个存储器件可以串行化状态信息，并以突发形式将其驱动在总线的子集M上。 每个存储器设备可以包括由存储器控制器初始化以定义其子集M的配置寄存器。
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