公开(公告)号：US11881483B2

公开(公告)日：2024-01-23

申请号：US17710979

申请日：2022-03-31

Applicant: iCometrue Company Ltd.

Inventor： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC: H01L27/11 ,  G11C11/44 ,  H01L27/118 ,  G11C14/00 ,  G11C5/04

CPC classification number: H01L27/11807 ,  G11C5/04 ,  G11C14/0081 ,  H01L2027/11838 ,  H01L2027/11875

Abstract: A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer.

公开(公告)号：US20230215839A1

公开(公告)日：2023-07-06

申请号：US18121873

申请日：2023-03-15

Applicant: iCometrue Company Ltd.

Inventor： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/16 ,  H10B80/00 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L24/16 ,  H01L23/481 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/32 ,  H01L24/73 ,  H01L25/16 ,  H01L25/18 ,  H01L25/0657 ,  H10B80/00 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06544 ,  H01L2924/1431

Abstract: A multi-chip package comprising an interconnection substrate; a first semiconductor IC chip over the interconnection substrate, wherein the first semiconductor IC chip comprises a first silicon substrate, a plurality of first metal vias passing through the first silicon substrate, a plurality of first transistors on a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection layer and the first silicon substrate and a first insulating dielectric layer over the first silicon substrate and between the first and second interconnection metal layers; a second semiconductor IC chip over and bonded to the first semiconductor IC chip; and a plurality of second metal vias over and coupling to the interconnection substrate, wherein the plurality of second metal vias are in a space extending from a sidewall of the first semiconductor IC chip.

公开(公告)号：US11651132B2

公开(公告)日：2023-05-16

申请号：US17351222

申请日：2021-06-17

Applicant: iCometrue Company Ltd.

Inventor： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC: G06F30/34 ,  H01L27/11524 ,  H01L27/112 ,  G06F3/06 ,  G11C7/10 ,  H03K19/1776 ,  G05B19/042 ,  G11C11/412 ,  H03K19/177 ,  H01L25/18 ,  H01L25/16

CPC classification number: G06F30/34 ,  G05B19/0423 ,  G06F3/0605 ,  G06F3/0659 ,  G11C7/106 ,  G11C7/1012 ,  G11C7/1045 ,  G11C11/412 ,  H01L25/16 ,  H01L25/18 ,  H01L27/11293 ,  H01L27/11524 ,  H03K19/177 ,  H03K19/1776 ,  G05B2219/15057 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2924/18162

Abstract: A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

公开(公告)号：US20230139263A1

公开(公告)日：2023-05-04

申请号：US17994466

申请日：2022-11-28

Applicant: iCometrue Company Ltd.

Inventor： Jin-Yuan Lee ,  Mou-Shiung Lin

IPC: H01L25/18 ,  H03K19/17736 ,  H03K19/17796 ,  H01L23/522 ,  H01L23/498 ,  H01L23/00 ,  H01L23/528 ,  H01L23/31 ,  H01L21/56

Abstract: A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.

公开(公告)号：US11600526B2

公开(公告)日：2023-03-07

申请号：US17155069

申请日：2021-01-21

Applicant: iCometrue Company Ltd.

Inventor： Jin-Yuan Lee ,  Mou-Shiung Lin

IPC: H01L21/768 ,  H01L21/78 ,  H01L21/48

Abstract: A method for a through-silicon-via (TSV) connector includes: providing a semiconductor wafer with a silicon substrate, wherein the semiconductor wafer has a frontside and a backside opposite to the frontside thereof; forming multiple holes in the silicon substrate of the semiconductor wafer; forming a first insulating layer at a sidewall and bottom of each of the holes; forming a metal layer over the semiconductor wafer and in each of the holes; polishing the metal layer outside each of the holes to expose a frontside surface of the metal layer in each of the holes; forming multiple metal bumps or pads each on the frontside surface of the metal layer in at least one of the holes; grinding a backside of the silicon substrate of the semiconductor wafer to expose a backside surface of the metal layer in each of the holes, wherein the backside surface of the metal layer in each of the holes and a backside surface of the silicon substrate of the semiconductor wafer are coplanar; and cutting the semiconductor wafer to form multiple through-silicon-via (TSV) connectors.

公开(公告)号：US11232562B2

公开(公告)日：2022-01-25

申请号：US17073353

申请日：2020-10-18

Applicant: iCometrue Company Ltd.

Inventor： Jin-Yuan Lee ,  Mou-Shiung Lin

IPC: G06K9/00 ,  G06T7/00 ,  G16H30/40 ,  A61B5/055 ,  A61B6/03 ,  A61B8/08 ,  A61B10/00 ,  G06N20/00

Abstract: A method for obtaining a probability in a 3D probability map, includes: obtaining at least one value of at least one parameter for each stop of a 3D moving window, wherein a first, second, third and fourth of the stops are partially overlapped, the first and second stops are shifted from each other by a distance equal to a first dimension of a computation voxel, the first and third stops are shifted from each other by a distance equal to a second dimension of the computation voxel, and the first and fourth stops are shifted from each other by a distance equal to a third dimension of the computation voxel; matching the at least one value to a classifier to obtain a first probability for each stop of the 3D moving window; and calculating a second probability for the computation voxel based on information associated with the first probabilities for the first through fourth stops.

公开(公告)号：US20210143124A1

公开(公告)日：2021-05-13

申请号：US17151634

申请日：2021-01-18

Applicant: iCometrue Company Ltd.

Inventor： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC: H01L23/00 ,  H01L23/522 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/17728 ,  H01L23/532 ,  H03K19/17704 ,  H01L23/538 ,  H01L25/065

Abstract: A multi-chip package comprising: an interconnection substrate comprising an interconnection bridge embedded in the interconnection substrate, and an interconnection scheme comprising a first interconnection metal layer, a second interconnection metal layer over the first interconnection layer and the interconnection bridge, and a polymer layer between the first and second interconnection metal layers, wherein the interconnection bridge is embedded in the interconnection scheme and has sidewalls surrounded by the polymer layer; a semiconductor IC chip over the interconnection substrate and across over an edge of the interconnection bridge; a memory chip over the interconnection substrate and across over an edge of the interconnection bridge, wherein the interconnection bridge comprises a plurality of metal interconnects configured for a data bus coupling the semiconductor IC chip to the memory chip, wherein a bitwidth of the data bus between the semiconductor IC chip and the memory chip is greater than or equal to 512.

公开(公告)号：US20210090983A1

公开(公告)日：2021-03-25

申请号：US17026186

申请日：2020-09-19

Applicant: iCometrue Company Ltd.

Inventor： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC: H01L23/498

Abstract: A chip package includes a first interconnection scheme; a plurality of first metal contacts under and on the first interconnection scheme and at a bottom surface of the chip package; a first semiconductor IC chip over the first interconnection scheme; a first connector over the first interconnection scheme and at a same horizontal level as the first semiconductor IC chip, wherein the first connector comprises a first substrate and a plurality of first through vias vertically extending through the first substrate of the first connector; a first polymer layer over the first interconnection scheme, wherein the first polymer layer has a top surface coplanar with a top surface of the first semiconductor IC chip, a top surface of the first substrate of the first connector and a top surface of each of the plurality of first through vias; and a second interconnection scheme on the top surface of the first polymer layer, the top surface of the first semiconductor IC chip, the top surface of the first connector and the top surface of each of the plurality of first through vias, wherein the second interconnection scheme comprises a plurality of second metal contacts at a top surface of the chip package.

公开(公告)号：US20210043557A1

公开(公告)日：2021-02-11

申请号：US16984663

申请日：2020-08-04

Applicant: iCometrue Company Ltd.

Inventor： Jin-Yuan Lee ,  Mou-Shiung Lin

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L23/00

Abstract: A chip package includes a first integrated-circuit (IC) chip; a second integrated-circuit (IC) chip over the first integrated-circuit (IC) chip; a connector over the first integrated-circuit (IC) chip and on a same horizontal level as the second integrated-circuit (IC) chip, wherein the connector comprises a substrate over the first integrated-circuit (IC) chip and a plurality of through vias vertically extending through the substrate of the connector; a polymer layer over the first integrated-circuit (IC) chip, wherein the polymer layer has a portion between the second integrated-circuit (IC) chip and connector, wherein the polymer layer has a top surface coplanar with a top surface of the second integrated-circuit (IC) chip, a top surface of the substrate of the connector and a top surface of each of the plurality of through vias; and an interconnection scheme on the top surface of the polymer layer, the top surface of the second integrated-circuit (IC) chip, the top surface of the connector and the top surface of each of the plurality of through vias.

公开(公告)号：US20210005592A1

公开(公告)日：2021-01-07

申请号：US16918909

申请日：2020-07-01

Applicant: iCometrue Company Ltd.

Inventor： Jin-Yuan Lee ,  Mou-Shiung Lin

IPC: H01L25/18 ,  H01L23/538 ,  H03K19/17728 ,  H03K19/1776

Abstract: A multichip package comprising: a first chip package comprising a first semiconductor IC chip, a first polymer layer in a space beyond and extending from a sidewall of the first semiconductor IC chip, a first through package via in the first polymer layer, and a first interconnection scheme under the first semiconductor IC chip, first polymer layer and first through package via, wherein the first semiconductor IC chip comprises a plurality of volatile memory cells configured to store first data associated with a plurality of resulting values for a look-up table (LUT) and a selection circuit configured to select, in accordance with a first input data set thereof, a data from a second input data set thereof as an output data for the logic operation; a first metal bump under the first chip package; and a non-volatile memory IC chip over the first chip package, wherein the non-volatile memory IC chip comprises a plurality of first non-volatile memory cells configured to store second data associated with the plurality of resulting values for the look-up table (LUT), wherein the first data are associated with the second data.