公开(公告)号：US09313017B1

公开(公告)日：2016-04-12

申请号：US14737330

申请日：2015-06-11

Applicant: Xilinx, Inc.

Inventor： Yu Liao ,  Geoffrey Zhang ,  Hongtao Zhang ,  Zhaoyin D. Wu ,  Kun-Yung Chang

IPC: H04L7/00 ,  H04L7/033

CPC classification number: H04L7/0087 ,  H04L7/0025 ,  H04L7/0062 ,  H04L25/03

Abstract: In an example, a clock data recovery (CDR) circuit for a receiver includes a timing error detector circuit, a loop filter, and a phase interpolator. The timing error detector circuit is coupled to receive, at a baud-rate, data samples and error samples for symbols received by the receiver. The timing error detector circuit is operable to generate both a timing error value and an estimated waveform value per symbol based on the data samples and the error samples. The loop filter is coupled to the timing error detector to receive timing error values. The phase interpolator is coupled to the loop filter to receive filtered timing error values, the phase interpolator operable to generate a control signal to adjust a sampling phase used to generate the data samples and the error samples.

Abstract translation: 在一个示例中，用于接收机的时钟数据恢复（CDR）电路包括定时误差检测器电路，环路滤波器和相位内插器。 定时误差检测器电路被耦合以以波特率接收由接收器接收的符号的数据样本和误差样本。 定时误差检测器电路可操作以基于数据样本和误差样本同时产生每个符号的定时误差值和估计波形值。 环路滤波器耦合到定时误差检测器以接收定时误差值。 相位内插器耦合到环路滤波器以接收滤波的定时误差值，相位插值器可操作以产生控制信号以调整用于生成数据样本和误差采样的采样相位。

公开(公告)号：US09237047B1

公开(公告)日：2016-01-12

申请号：US14689294

申请日：2015-04-17

Applicant: Xilinx, Inc.

Inventor： Hongtao Zhang ,  Geoffrey Zhang ,  Patrick Satarzadeh ,  Zhaoyin D. Wu

IPC: H04L27/06 ,  H04B1/12

CPC classification number: H04L27/06 ,  H04L25/061

Abstract: A circuit for receiving data in an integrated circuit is described. The circuit comprises a receiver configured to receive an input signal and to generate output data based upon the input signal, the receiver having a level detection circuit coupled to receive the input signal; and a calibration circuit coupled to the receiver, the calibration circuit having an input for receiving the input signal; an error detection circuit coupled to the input, the error detection circuit coupled to receive the input signal, a first reference voltage and a second reference voltage; and a control circuit coupled to an output of the error detection circuit, wherein the control circuit selectively generates either an offset control signal or an amplitude control signal based upon comparisons of the input signal to the first reference voltage and the second reference voltage. A method of receiving data is also disclosed.

Abstract translation: 描述了用于在集成电路中接收数据的电路。 该电路包括接收器，配置为接收输入信号并基于输入信号产生输出数据，接收器具有耦合以接收输入信号的电平检测电路; 以及校准电路，其耦合到所述接收器，所述校准电路具有用于接收所述输入信号的输入; 耦合到所述输入端的误差检测电路，所述误差检测电路被耦合以接收所述输入信号，第一参考电压和第二参考电压; 以及耦合到所述误差检测电路的输出的控制电路，其中所述控制电路基于所述输入信号与所述第一参考电压和所述第二参考电压的比较来选择性地产生偏移控制信号或幅度控制信号。 还公开了接收数据的方法。

公开(公告)号：US11894959B2

公开(公告)日：2024-02-06

申请号：US17873002

申请日：2022-07-25

Applicant: XILINX, INC.

Inventor： Ronan Sean Casey ,  Lokesh Rajendran ,  Declan Carey ,  Kevin Zheng ,  Catherine Hearne ,  Hongtao Zhang

IPC: H04L25/49 ,  H04L27/04

CPC classification number: H04L25/4917 ,  H04L27/04

Abstract: Methods, systems, and apparatus described herein make a multi-level PAM signal (PAM-N signal) at a transmitter using CMOS-based components. By forming the PAM-N signal at the transmitter, receivers do not have to recombine and/or realign multiple signals and only employs a single transmission line channel (or two transmission line channels in differential implementations) to convey the data stream to the receiver from the transmitter.

公开(公告)号：US11522735B1

公开(公告)日：2022-12-06

申请号：US16998864

申请日：2020-08-20

Applicant: Xilinx, Inc.

Inventor： Kevin Zheng ,  Hongtao Zhang ,  Geoffrey Zhang

IPC: H04L25/03 ,  H03H21/00

Abstract: Apparatus and associated methods relate to an ADC-based digital receiver including a feedforward equalizer (FFE) that has m precursor taps and n postcursor taps to equalize the precursor portion, and to adapt postcursor intersymbol interference (ISI) through a predetermined equalization coefficient selected to counteract the noise boosting effect associated with the precursor equalization. In an illustrative example, the receiver may dynamically balance noise and ISI through adaptively determining a coefficient hp1 of a first postcursor tap of a first FFE and a coefficient h1 of a first postcursor tap of a second equalizer adapted to substantially reduce or eliminate additional ISI introduced by the first FFE. The first FFE may optimize ISI removal and noise reduction, for example. One of the coefficients h1 and hp1 may be predetermined, and then the other coefficient may be iteratively adapted to trade off precursor ISI and postcursor ISI to minimize BER.

公开(公告)号：US10404408B1

公开(公告)日：2019-09-03

申请号：US15377780

申请日：2016-12-13

Applicant: Xilinx, Inc.

Inventor： Winson Lin ,  Hongtao Zhang ,  Yu Xu ,  Geoffrey Zhang

IPC: H04L1/00 ,  H04L27/02 ,  H04L27/01 ,  H04L27/34

Abstract: An example method of capturing an error distribution data for a serial channel includes: receiving a signal from the serial channel at a receiver in an integrated circuit (IC), the signal encoding data using pulse amplitude modulation (PAM) scheme having more than two levels; determining a plurality of symbols from the signal, each of the plurality of symbols encoding a plurality of bits; comparing the plurality of symbols with a plurality of expected symbols to detect a plurality of symbol errors; generating the error distribution data by accumulating numbers of the plurality of symbol errors across a plurality of bins based error type; and transmitting the error distribution data from the receiver to a computing system for processing.

公开(公告)号：US09595990B1

公开(公告)日：2017-03-14

申请号：US15158420

申请日：2016-05-18

Applicant: Xilinx, Inc.

Inventor： Hongtao Zhang ,  Geoffrey Zhang

IPC: H04L27/06 ,  H04B1/12 ,  H03G3/20

CPC classification number: H04L25/03878 ,  H03G3/3078

Abstract: A circuit for enabling an adaptation of an automatic gain control circuit comprises an automatic gain control (ACG) circuit configured to receive an input signal and to generate a boosted input signal. An average peak signal magnitude adaptation circuit is configured to receive an output of a decision circuit and to generate an average peak signal magnitude. An average peak signal target calculation circuit is configured to receive the average peak signal magnitude and detected peak signal magnitudes, wherein the average peak signal magnitude adaptation circuit generates a target peak signal magnitude. An AGC adaptation circuit is configured to receive an average peak signal magnitude and the target peak signal magnitude, wherein the AGC adaptation circuit provides an AGC control signal to the AGC circuit to maximize the effective signal magnitude within an acceptable linearity range.

Abstract translation: 用于实现自动增益控制电路的自适应的电路包括被配置为接收输入信号并产生升压的输入信号的自动增益控制（ACG）电路。 平均峰值信号幅度自适应电路被配置为接收判定电路的输出并产生平均峰值信号幅度。 平均峰值信号目标计算电路被配置为接收平均峰值信号幅度和检测到的峰值信号幅度，其中平均峰值信号幅度适配电路产生目标峰值信号幅度。 AGC适配电路被配置为接收平均峰值信号幅度和目标峰值信号幅度，其中AGC适配电路向AGC电路提供AGC控制信号，以使可接受的线性范围内的有效信号幅度最大化。

公开(公告)号：US09455848B1

公开(公告)日：2016-09-27

申请号：US14829318

申请日：2015-08-18

Applicant: Xilinx, Inc.

Inventor： Hongtao Zhang ,  Geoffrey Zhang ,  Kun-Yung Chang

IPC: H04L25/03 ,  H04L7/00

CPC classification number: H04L25/03057 ,  H04L7/0025 ,  H04L7/0062 ,  H04L7/0087 ,  H04L2025/03611

Abstract: In an example, an apparatus for clock data recovery (CDR) in a receiver includes a decision feedback equalizer (DFE) having a data slicer providing data samples, an error slicer providing error samples, and an offset error slicer providing offset error samples, the offset error slicer operable to set its threshold based on an offset first post-cursor coefficient. The apparatus further includes a CDR circuit operable to control a sampling clock for the data slicer, the error slicer, and the offset error slicer based on the data samples and the offset error samples.

Abstract translation: 在一个示例中，接收机中用于时钟数据恢复（CDR）的装置包括具有提供数据样本的数据限幅器的判定反馈均衡器（DFE），提供误差采样的误差限幅器和提供偏移误差采样的偏移误差限幅器， 偏移误差限幅器，其可操作以基于偏移的第一后置光标系数来设置其阈值。 该装置还包括CDR电路，其可操作以基于数据样本和偏移误差样本来控制数据限幅器，误差限幅器和偏移误差限幅器的采样时钟。

公开(公告)号：US09178552B1

公开(公告)日：2015-11-03

申请号：US14547394

申请日：2014-11-19

Applicant: Xilinx, Inc.

Inventor： Patrick Satarzadeh ,  Hongtao Zhang ,  Geoffrey Zhang ,  Zhaoyin D. Wu

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04B1/16 ,  H04L25/03

CPC classification number: H04L25/03885 ,  H04B1/16 ,  H04L25/03057 ,  H04L2025/03547

Abstract: In a method for channel adaptation, an analog input signal is received with a bimodal receiver via a communications channel. The analog input signal is converted to a digital input signal with an analog-to-digital converter of a digital receiver of the bimodal receiver. Channel coefficients are detected for the digital input signal associated with the communications channel. The channel coefficients indicate a number of post-cursor taps of the bimodal receiver to be used to provide an equalized digital output signal from the digital input signal. It is determined whether the number of post-cursor taps or a value associated therewith is equal to or less than a threshold number. A switch from the receiving of the analog input signal by the digital receiver to an analog receiver of the bimodal receiver is made to provide the equalized digital output signal for the analog input signal.

Abstract translation: 在一种用于信道适配的方法中，通过通信信道用双模接收机接收模拟输入信号。 模拟输入信号通过双模接收器的数字接收器的模数转换器转换为数字输入信号。 检测与通信信道相关联的数字输入信号的信道系数。 信道系数指示用于从数字输入信号提供均衡的数字输出信号的双模接收机的多个后置光标抽头。 确定后视标抽头的数量或与其相关联的值是否等于或小于阈值数。 使得从数字接收机将模拟输入信号接收到双模接收机的模拟接收机的切换是为模拟输入信号提供均衡的数字输出信号。