公开(公告)号：US20080012743A1

公开(公告)日：2008-01-17

申请号：US11829157

申请日：2007-07-27

申请人： Li-Te Wu ,  Wei-Chan Hsu

发明人： Li-Te Wu ,  Wei-Chan Hsu

IPC分类号： H03M3/02

CPC分类号： H04S3/02

摘要： The invention provides a method for mixing signals with an analog-to-digital converter. The analog-to-digital converter receives a plurality of analog signals. First, the plurality of analog signals are respectively converted to a plurality of first datastreams with a plurality of first delta-sigma modulators. The plurality of first datastreams are then mixed to generate at least one second datastream. The at least one second datastream is then converted to at least one third datastream with at least one second delta-sigma modulator. The at least one second delta-sigma modulator and the plurality of first delta-sigma modulators are triggered by the same clock signal.

摘要翻译： 本发明提供了一种用于将信号与模数转换器混合的方法。 模数转换器接收多个模拟信号。 首先，多个模拟信号分别被转换成具有多个第一Δ-Σ调制器的多个第一数据流。 然后将多个第一数据流混合以产生至少一个第二数据流。 然后将至少一个第二数据流转换成具有至少一个第二Δ-Σ调制器的至少一个第三数据流。 所述至少一个第二Δ-Σ调制器和所述多个第一Δ-Σ调制器由相同的时钟信号触发。

公开(公告)号：US08804379B2

公开(公告)日：2014-08-12

申请号：US13012261

申请日：2011-01-24

申请人： Wei-Chan Hsu ,  Chong-Hock Yeam ,  Siang-Yu Yang

发明人： Wei-Chan Hsu ,  Chong-Hock Yeam ,  Siang-Yu Yang

IPC分类号： H02M3/335 ,  H02M1/00

CPC分类号： H02M3/33507 ,  H02M2001/0032 ,  Y02B70/16

摘要： A flyback converter system and feedback controlling apparatus and method of operating the same are disclosed. The feedback controlling apparatus for the flyback converter system includes a primary feedback loop unit for generating a primary feedback signal, and a secondary feedback loop unit for generating a secondary feedback signal, a loop selector. In light-load conditions, the loop selector supplies the primary feedback signal to a PWM controller for feedback control, and the secondary feedback loop unit is disabled by a power monitor to save electrical energy.

摘要翻译： 公开了一种反激式转换器系统及其反馈控制装置及其操作方法。 用于回扫转换器系统的反馈控制装置包括用于产生主反馈信号的主反馈回路单元和用于产生次级反馈信号的次级反馈回路单元，循环选择器。 在轻负载条件下，环路选择器将主反馈信号提供给PWM控制器进行反馈控制，并通过功率监视器禁用次级反馈环路单元以节省电能。

公开(公告)号：US06472933B2

公开(公告)日：2002-10-29

申请号：US09407102

申请日：1999-09-27

申请人： Wei-Chan Hsu

发明人： Wei-Chan Hsu

IPC分类号： H03F338

CPC分类号： H03F3/2173 ,  H03F2200/331

摘要： Invention resides in a switching amplifier having a quaternary input control signal that provides quaternary levels (1, 0H, −1, and 0L) which is coupled to an H-bridge amplifier to provide error cancellation in switching amplifier output signal. The quaternary control signal alternates from a zero state at a high level (“0H”) to a zero state at a low level (“0L”) between each non-zero state (+1 or −1). In a preferred embodiment, a three-level sigma-delta modulator is provided for greater operational efficiency for ease of detecting zero states and minimizing power. The three-level sigma-delta modulator receives and converts an amplifier input signal into a ternary output signal that is then coupled to a ternary-to-quaternary converter to generate the quaternary control signal to provide as input to the H-bridge.

摘要翻译： 发明内容在具有四进制输入控制信号的开关放大器，其提供耦合到H桥放大器以提供开关放大器输出信号中的误差消除的四级电平（1,0H，-1和0L）。 四级控制信号在每个非零状态（+1或-1）之间以高电平（“0H”）的零状态交替为低电平（“0L”）的零状态。 在优选实施例中，提供三电平Σ-Δ调制器用于更高的操作效率，以便于检测零状态并使功率最小化。 三电平Σ-Δ调制器接收并将放大器输入信号转换为三元输出信号，然后将其耦合到三进制转换器以产生四进制控制信号以提供到H桥的输入。

公开(公告)号：US5272432A

公开(公告)日：1993-12-21

申请号：US691712

申请日：1991-05-01

申请人： Chinh D. Nguyen ,  Wei-Chan Hsu

发明人： Chinh D. Nguyen ,  Wei-Chan Hsu

IPC分类号： G05F3/26 ,  H02J1/02 ,  H03K17/16 ,  H03M1/06 ,  H03M1/08 ,  H03M1/66 ,  G05F3/16

CPC分类号： H03M1/0631 ,  H03M1/0863

摘要： In a digital-to-analog converter (DAC) current source including a current mirror, an output transistor biased by a reference voltage and a steering transistor, a structure and a method are provided to implement the DAC current source without current spikes in the output current. Current spikes in the output current are avoided by including a transistor acting as a low-pass filter between the steering transistor and the output transistor. In one embodiment, the DAC current source circuit is implemented by PMOS transistors.

公开(公告)号：US5214608A

公开(公告)日：1993-05-25

申请号：US691711

申请日：1991-05-01

申请人： Wei-Chan Hsu ,  Wei-Kuang J. Chiu

发明人： Wei-Chan Hsu ,  Wei-Kuang J. Chiu

IPC分类号： G09G5/00 ,  G09G5/04 ,  G09G5/06 ,  G11C7/06 ,  G11C7/16 ,  G11C11/401

CPC分类号： G11C7/062 ,  G11C7/16

摘要： A dual sense amplifier structure and a method are provided in a RAMDAC, to allow the video path to be probed digitally during testing. Each of the two sets of sense amplifiers in the dual sense amplifier structure can be individually enabled to provide the same output data to both a color value register accessible over a data port and the digital-to-analog converters for interface with an analog display. In one embodiment, the sense amplifiers which provide color values to a data port interfaced with the CPU are implemented by simpler circuits than the sense amplifiers which used to provide the color values to the DACs.

公开(公告)号：US08102015B2

公开(公告)日：2012-01-24

申请号：US12244168

申请日：2008-10-02

申请人： Shih-Chin Gong ,  Wei-Chan Hsu

发明人： Shih-Chin Gong ,  Wei-Chan Hsu

IPC分类号： H01L29/84 ,  H04R9/08

CPC分类号： H04R1/04 ,  B81B2201/0257 ,  B81C1/0023 ,  B81C2203/0109 ,  B81C2203/032 ,  B81C2203/035 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2924/1461 ,  H01L2924/3011 ,  H01L2924/3025 ,  H04R19/005 ,  H01L2924/00

摘要： A microphone package includes a carrier, a cap, an integrated circuit chip, and a microphone unit. The cap covers the carrier to form a storage space. The integrated circuit chip is disposed in the storage space. The microphone unit is disposed in the storage space and stacked on the integrated circuit chip.

摘要翻译： 麦克风封装包括载体，盖，集成电路芯片和麦克风单元。 盖子覆盖载体以形成存储空间。 集成电路芯片设置在存储空间中。 麦克风单元设置在存储空间中并堆叠在集成电路芯片上。

公开(公告)号：US08885364B2

公开(公告)日：2014-11-11

申请号：US13432921

申请日：2012-03-28

申请人： Kuan-Sheng Wang ,  Wei-Chan Hsu ,  Jan-He Li

发明人： Kuan-Sheng Wang ,  Wei-Chan Hsu ,  Jan-He Li

IPC分类号： H02M3/335 ,  H02M1/00

CPC分类号： H02M3/33523 ,  H02M2001/0032 ,  Y02B70/16

摘要： A flyback converter with primary side and secondary side feedback control includes a transformer, a secondary-side feedback unit and a feedback control unit. The secondary-side feedback unit is electrically connected to a secondary winding of the transformer and comprises an isolated signal transceiver device and an error amplifier. The feedback control unit is electrically connected to an auxiliary winding of the transformer and operatively connected to the isolated signal transceiver device. When the flyback converter is operated in heavy load conditions, the feedback control unit receives a secondary feedback control signal sent from the isolated signal transceiver device for feedback control. When the flyback converter is operated in light load conditions, the feedback control unit receives a primary feedback control signal sensed by the auxiliary winding for feedback control.

摘要翻译： 具有初级侧和次级侧反馈控制的反激式转换器包括变压器，次级侧反馈单元和反馈控制单元。 次级侧反馈单元电连接到变压器的次级绕组，并且包括隔离信号收发器装置和误差放大器。 反馈控制单元电连接到变压器的辅助绕组并可操作地连接到隔离信号收发器装置。 当反激式转换器在重载条件下工作时，反馈控制单元接收从隔离信号收发器装置发送的用于反馈控制的次级反馈控制信号。 当反激转换器在轻负载条件下工作时，反馈控制单元接收由辅助绕组感测的主反馈控制信号以进行反馈控制。

公开(公告)号：US06768359B2

公开(公告)日：2004-07-27

申请号：US10279972

申请日：2002-10-25

申请人： Wei-Chan Hsu

发明人： Wei-Chan Hsu

IPC分类号： H03L700

CPC分类号： H03L7/0895 ,  H03L7/087

摘要： A charge-pump phase-locked loop (CP-PLL) circuit with charge calibration. The CP-PLL circuit keeps the phase of an output clock signal constant in a “locked” condition, and includes a charge-pump circuit and a calibration circuit. The charge-pump circuit provides a charge-pump output current. The charge-pump circuit also includes a transistor configured to fine tune the charge-pump output current based on a calibrate voltage signal to eliminate a net charge delivered from the charge-pump output current. The calibration circuit senses the net charge and generates the calibrate voltage signal having a value in proportion to an amount of the net charge. Under control of the calibrate voltage signal, the charge-pump circuit cooperating with the transistor regulates the net charge to become exactly zero, thereby maintaining the phase of the output clock signal locked onto the phase of the reference clock signal.

摘要翻译： 带有电荷校准的电荷泵锁相环（CP-PLL）电路。 CP-PLL电路使输出时钟信号的相位保持恒定在“锁定”状态，并且包括电荷泵电路和校准电路。 电荷泵电路提供电荷泵输出电流。 电荷泵电路还包括晶体管，其配置为基于校准电压信号微调电荷泵输出电流，以消除从电荷泵输出电流传递的净电荷。 校准电路感测净电荷并产生具有与净电荷量成比例的值的校准电压信号。 在校准电压信号的控制下，与晶体管协调的电荷泵电路调节净电荷变为正好为零，从而保持输出时钟信号的相位锁定在参考时钟信号的相位上。

公开(公告)号：US06608511B1

公开(公告)日：2003-08-19

申请号：US10196182

申请日：2002-07-17

申请人： Wei-Chan Hsu

发明人： Wei-Chan Hsu

IPC分类号： H03L700

CPC分类号： H03L7/0895 ,  H03L7/087

摘要： A charge-pump phase-locked loop (PLL) circuit with charge calibration. The PLL keeps the phase of an output clock signal constant in a “locked” condition, and includes a first charge pump, a second charge pump and a charge sensing circuit. The first and the second charge pumps provide a first current and a second current, respectively. According to a first and second net charge delivered from the first and the second currents separately, the charge sensing circuit provides a calibrate voltage signal as feedback to the first charge pump and the second charge pump. Under control of the calibrate voltage signal, the first and the second charge pumps regulate the first net charge and the second net charge to become exactly zero thereby maintaining the phase of the output clock signal locked onto the phase of a reference clock signal.

摘要翻译： 带有电荷校准的电荷泵锁相环（PLL）电路。 PLL保持输出时钟信号的相位恒定在“锁定”状态，并且包括第一电荷泵，第二电荷泵和电荷感测电路。 第一和第二电荷泵分别提供第一电流和第二电流。 根据分别从第一和第二电流传送的第一和第二净电荷，电荷感测电路提供校准电压信号作为对第一电荷泵和第二电荷泵的反馈。 在校准电压信号的控制下，第一和第二电荷泵调节第一净电荷和第二净电荷变为正好为零，从而将输出时钟信号的相位锁定在参考时钟信号的相位上。

公开(公告)号：US5748126A

公开(公告)日：1998-05-05

申请号：US612691

申请日：1996-03-08

申请人： Chingwo Ma ,  Inging Yang ,  Wei-Chan Hsu

发明人： Chingwo Ma ,  Inging Yang ,  Wei-Chan Hsu

IPC分类号： H03M1/08 ,  G06J1/00 ,  H03H17/00 ,  H03H17/02 ,  H03M1/66 ,  H03M3/02 ,  H03M7/32 ,  H03M3/00

CPC分类号： G06J1/00 ,  H03M3/508

摘要： A conversion system and method is disclosed for converting between digital and analog data signals. The conversion system comprises a signal input line for each digital data signal, a reconstructor-resampler unit for each digital data signal, a combiner, a modulator, a digital-to-analog converter, and a signal output line. Each signal line input couples to the respective reconstructor-resampler unit for the digital data signal. Each reconstructor-resampler unit then couples to a combiner which couples to a modulator. The modulator couples to the digital-to-analog converter that couples to the signal output line from which an analog output signal is produced. The reconstructor-resampler comprises a sampling member coupled to the signal line input and a polynomial interpolator member coupled to the sampling member and the modulator. Also, the modulator operates at a predetermined, or fixed, frequency regardless of the sampling frequency of the digital data signal. The steps of the conversion method include inputting a digital data signal having a sampling frequency, reconstructing and resampling the digital data signal to generate a resampled data signal, performing noise-shaping on the resampled data signal to generate a x-bit data signal from a modulator operating at a predetermined frequency regardless of the sampling frequency of any of the digital data signals, and converting the x-bit data signal to an analog data signal. In addition, an analog-to-digital conversion system and method is disclosed that comprises a signal line input, a decimator, a reconstructor-resampler a signal output line, and a modulator operating at a predetermined frequency to convert an analog data signal to a digital data signal.

摘要翻译： 公开了用于在数字和模拟数据信号之间转换的转换系统和方法。 转换系统包括用于每个数字数据信号的信号输入线，每个数字数据信号的重建器重新采样器单元，组合器，调制器，数模转换器和信号输出线。 每个信号线输入耦合到数字数据信号的相应的重构器 - 重新采样器单元。 然后，每个重建器重新采样器单元耦合到耦合到调制器的组合器。 调制器耦合到数模转换器，耦合到产生模拟输出信号的信号输出线。 重构器重新采样器包括耦合到信号线输入的采样部件和耦合到采样部件和调制器的多项式内插器部件。 而且，无论数字数据信号的采样频率如何，调制器以预定的或固定的频率工作。 转换方法的步骤包括输入具有采样频率的数字数据信号，重构和再采样数字数据信号以产生重采样的数据信号，对重新采样的数据信号执行噪声整形，以产生来自 调制器以任何数字数据信号的采样频率而以预定频率工作，并将x位数据信号转换为模拟数据信号。 此外，公开了一种模数转换系统和方法，其包括信号线输入，抽取器，重建器 - 重采样器，信号输出线和以预定频率工作的调制器，以将模拟数据信号转换为 数字数据信号。