公开(公告)号：US11676864B2

公开(公告)日：2023-06-13

申请号：US17005172

申请日：2020-08-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuan-Ting Pan ,  Kuo-Cheng Chiang ,  Shi-Ning Ju ,  Shang-Wen Chang ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/823425 ,  H01L21/823481 ,  H01L27/0886

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first fin, a second fin adjacent the first fin, and a third fin adjacent the second fin. The structure further includes a first source/drain epitaxial feature merged with a second source/drain epitaxial feature. The structure further includes a third source/drain epitaxial feature, and a first liner positioned at a first distance away from a first plane defined by a first sidewall of the first fin and a second distance away from a second plane defined by a second sidewall of the second fin. The first distance is substantially the same as the second distance, and the merged first and second source/drain epitaxial features is disposed over the first liner. The structure further includes a dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature.

公开(公告)号：US20220375860A1

公开(公告)日：2022-11-24

申请号：US17815119

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Ching-Wei Tsai ,  Cheng-Ting Chung ,  Cheng-Chi Chuang ,  Shang-Wen Chang

IPC: H01L23/528 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a substrate having a front side and a back side; a gate stack formed on the front side of the substrate and disposed on an active region of the substrate; a first source/drain feature formed on the active region and disposed at an edge of the gate stack; a backside power rail formed on the back side of the substrate; and a backside contact feature interposed between the backside power rail and the first source/drain feature, and electrically connecting the backside power rail to the first source/drain feature. The backside contact feature further includes a first silicide layer on the back side of the substrate and directly contacting a bottom surface of the first source/drain feature.

公开(公告)号：US11437385B2

公开(公告)日：2022-09-06

申请号：US16526415

申请日：2019-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Wang ,  Yi-Hsun Chiu ,  Yi-Hsiung Lin ,  Shang-Wen Chang

IPC: H01L27/11 ,  H01L27/088 ,  H01L29/417 ,  H01L21/762 ,  H01L29/423 ,  G11C11/412

Abstract: A static random access memory (SRAM) cell includes a first p-type semiconductor fin, a first dielectric fin, a first hybrid fin, a second hybrid fin, a second dielectric fin, and a second p-type semiconductor fin disposed in this order along a first direction and oriented lengthwise along a second direction, where each of the first and the second hybrid fins has a first portion including an n-type semiconductor material and a second portion including a dielectric material. The SRAM cell further includes n-type source/drain (S/D) epitaxial features disposed over each of the first and the second p-type semiconductor fins, p-type S/D epitaxial features disposed over the first portion of each of the first and the second hybrid fins, and S/D contacts physically contacting each of the p-type S/D epitaxial features and the second portion of each of the first and the second hybrid fins.

公开(公告)号：US20220262794A1

公开(公告)日：2022-08-18

申请号：US17733169

申请日：2022-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsun Chiu ,  Ching-Wei Tsai ,  Yu-Xuan Huang ,  Cheng-Chi Chuang ,  Shang-Wen Chang

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/423 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66 ,  H01L23/535

Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.

公开(公告)号：US20210202465A1

公开(公告)日：2021-07-01

申请号：US16727731

申请日：2019-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Wang ,  Shang-Wen Chang ,  Min Cao

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238

Abstract: The disclosed circuit includes a first and a second active region (AR) spaced a spacing S along a direction in a first standard cell (SC) that spans D1 along the direction between a first and a second cell edge (CE). Each of the first and second ARs spans a first width W1 along the direction; a third and a fourth AR spaced S in a second SC that spans a second dimension Ds along the direction between a third and a fourth CE; and gate stacks extend from the fourth CE of the second SC to the first CE of the first SC, wherein Ds

公开(公告)号：US20200006160A1

公开(公告)日：2020-01-02

申请号：US16393543

申请日：2019-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Yi-Hsun Chiu ,  Shang-Wen Chang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/768 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L23/522

Abstract: A method includes forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, where the first epitaxial S/D feature is disposed adjacent to the second epitaxial S/D feature, forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature, removing a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature to form a first trench, removing a remaining portion of the dummy contact feature to form a second trench, and forming a metal S/D contact in the first and the second trenches.

公开(公告)号：US12237233B2

公开(公告)日：2025-02-25

申请号：US17738928

申请日：2022-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Yi-Hsun Chiu ,  Shang-Wen Chang ,  Ching-Wei Tsai ,  Chih-Hao Wang

IPC: H01L21/66 ,  G01R31/3183 ,  H01L23/522 ,  H01L23/528

Abstract: Semiconductor devices and methods are provided which facilitate performing physical failure analysis (PFA) testing from a backside of the devices. In at least one example, a device is provided that includes a semiconductor device layer including a plurality of diffusion regions. A first interconnection structure is disposed on a first side of the semiconductor device layer, and the first interconnection structure includes at least one electrical contact. A second interconnection structure is disposed on a second side of the semiconductor device layer, and the second interconnection structure includes a plurality of backside power rails. Each of the backside power rails at least partially overlaps a respective diffusion region of the plurality of diffusion regions and defines openings which expose portions of the respective diffusion region at the second side of the semiconductor device layer.

公开(公告)号：US20250046700A1

公开(公告)日：2025-02-06

申请号：US18495495

申请日：2023-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Cheng-Chi Chuang ,  Ching-Wei Tsai ,  Shang-Wen Chang

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A method includes forming a first device die and a second device die. The first device die includes a first integrated circuit, and a first bond pad at a first surface of the first device die. The first integrated circuit is electrically connected to the first bond pad. The second device die includes a power switch that includes a first source/drain region, a second source/drain region, a second bond pad electrically connecting to the first source/drain region, and a third bond pad electrically connecting to the second source/drain region. The method further includes bonding the first device die with the second device die to form a package, with the first bond pad bonding to the third bond pad, and bonding the package to a package component.

公开(公告)号：US20240363626A1

公开(公告)日：2024-10-31

申请号：US18766867

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsun Chiu ,  Ching-Wei Tsai ,  Yu-Xuan Huang ,  Cheng-Chi Chuang ,  Shang-Wen Chang

IPC: H01L27/088 ,  H01L21/768 ,  H01L23/535 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/7682 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7851

Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.

公开(公告)号：US20240312913A1

公开(公告)日：2024-09-19

申请号：US18184085

申请日：2023-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Wen Chang ,  Cheng-Chi Chuang ,  Ching-Wei Tsai ,  Yi-Hsun Chiu ,  Yu-Xuan Huang

IPC: H01L23/528 ,  H01L21/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/5286 ,  H01L21/7806 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method includes forming a vertical transistor, and the method includes forming a vertical semiconductor bar over a substrate, forming a gate dielectric and a gate electrode encircling the vertical semiconductor bar, forming a first source/drain region over a top surface of the vertical semiconductor bar, removing the substrate to reveal a bottom surface of the vertical semiconductor bar; and forming a second source/drain region contacting the bottom surface of the vertical semiconductor bar. The method further includes forming a backside power line, with the backside power line being on a bottom side of the vertical semiconductor bar. The backside power line is connected to the second source/drain region.