公开(公告)号：US20230065234A1

公开(公告)日：2023-03-02

申请号：US17459476

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pinyen LIN ,  Chin-Hsiang LIN ,  Huang-Lin CHAO

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/3115

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second fin structures formed over the substrate, and an isolation structure between the first and second fin structures. The isolation structure can include a lower portion and an upper portion. The lower portion of the isolation structure can include a metal-free dielectric material. The upper portion of the isolation structure can include a metallic element and silicon.

公开(公告)号：US20220037500A1

公开(公告)日：2022-02-03

申请号：US17197892

申请日：2021-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Li WANG ,  Hsu-Kai CHANG ,  Jhih-Rong HUANG ,  Yen-Tien TUNG ,  Chia-Hung CHU ,  Tzer-Min SHEN ,  Pinyen LIN

IPC: H01L29/45 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a gate structure disposed on the fin structure, a source/drain (S/D) region disposed adjacent to the gate structure, a contact structure disposed on the S/D region, and a dipole layer disposed at an interface between the ternary compound layer and the S/D region. The contact structure includes a ternary compound layer disposed on the S/D region, a work function metal (WFM) silicide layer disposed on the ternary compound layer, and a contact plug disposed on the WFM silicide layer.

公开(公告)号：US20210013103A1

公开(公告)日：2021-01-14

申请号：US17033256

申请日：2020-09-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Chin CHANG ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/768 ,  H01L29/78 ,  H01L23/522 ,  H01L21/3213

Abstract: A semiconductor device includes a semiconductor substrate, a source/drain region, a source/drain contact, a conductive via and a first polymer layer. The source/drain region is in the semiconductor substrate. The source/drain contact is over the source/drain region. The source/drain via is over the source/drain contact. The first polymer layer extends along a first sidewall of the conductive via and is separated from a second sidewall of the conductive via substantially perpendicular to the first sidewall of the conductive via.

公开(公告)号：US20200335340A1

公开(公告)日：2020-10-22

申请号：US16921032

申请日：2020-07-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Chun HUANG ,  Chiu-Hsiang CHEN ,  Ya-Wen YEH ,  Yu-Tien SHEN ,  Po-Chin CHANG ,  Chien Wen LAI ,  Wei-Liang LIN ,  Ya Hui CHANG ,  Yung-Sung YEN ,  Li-Te LIN ,  Pinyen LIN ,  Ru-Gun LIU ,  Chin-Hsiang LIN

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265

Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.

公开(公告)号：US20200066872A1

公开(公告)日：2020-02-27

申请号：US16299531

申请日：2019-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Han-Yu LIN ,  Chansyun David YANG ,  Fang-Wei LEE ,  Tze-Chung LIN ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L29/78 ,  H01L21/768 ,  H01L21/311 ,  H01L21/321 ,  H01L29/06

Abstract: A method for forming a semiconductor device structure is provided. The method for forming a semiconductor device structure includes forming a fin structure over a substrate. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method for forming the semiconductor device structure also includes removing the first semiconductor layers of the fin structure in a channel region thereby exposing the second semiconductor layers of the fin structure. The method for forming the semiconductor device structure also includes forming a dielectric material surrounding the second semiconductor layers, and treating a first portion of the dielectric material. The method for forming the semiconductor device structure also includes etching the first portion of the dielectric material to form gaps, and filling the gaps with a gate stack.

公开(公告)号：US20190165133A1

公开(公告)日：2019-05-30

申请号：US16192566

申请日：2018-11-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Ruei JHAN ,  Yi-Lun CHEN ,  Fang-Wei LEE ,  Han-Yu LIN ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/033 ,  H01L21/768 ,  H01L21/311

Abstract: In some embodiments, a method is provided. Dummy gate stacks are formed over a semiconductor substrate. An interlayer dielectric (ILD) layer is formed over the dummy gate stacks. A first portion of the ILD layer over top surfaces of the dummy gate stacks is removed, such that a second portion of the ILD layer remains between the dummy gate stacks. The dummy gate stacks are replaced with metal gate stacks. Neutral NF3 radicals into the water are applied to etch the ILD layer.

公开(公告)号：US20190165132A1

公开(公告)日：2019-05-30

申请号：US16136339

申请日：2018-09-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen LO ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/033 ,  H01L21/027 ,  H01L21/321 ,  H01L29/423 ,  H01L21/308 ,  H01L21/768 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device, includes: forming a dummy gate structure on a semiconductor substrate; forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure; removing the dummy gate structure from the semiconductor substrate; forming a metal gate electrode on the semiconductor substrate and between the gate spacers; and performing a plasma etching process to the metal gate electrode, wherein the plasma etching process comprises performing in sequence a first non-zero bias etching step and a first zero bias etching step.

公开(公告)号：US20170151648A1

公开(公告)日：2017-06-01

申请号：US15158529

申请日：2016-05-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chi-Hao HUANG ,  Hsuan-Pang LIU ,  Yuan-Chun SIE ,  Pinyen LIN ,  Cheng-Chung CHIEN

IPC: B24B37/20

CPC classification number: B24B37/20 ,  B24B37/22 ,  B24B37/26 ,  B24D18/0045

Abstract: A polishing pad for a chemical-mechanical polishing apparatus includes a first support layer and a polishing layer. The polishing layer is present on the first support layer. The polishing layer has a top surface that faces away from the first support layer and at least one first cavity that is buried at least beneath the top surface of the polishing layer.

公开(公告)号：US20240405093A1

公开(公告)日：2024-12-05

申请号：US18328502

申请日：2023-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shen-Yang LEE ,  Hsiang-Pi CHANG ,  Huang-Lin CHAO ,  Pinyen LIN

IPC: H01L29/51 ,  H01L21/3115 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: The present disclosure describes forming a crystalline high-k dielectric layer at a reduced crystallization temperature in a semiconductor device. The method includes forming a channel structure on a substrate, forming an interfacial layer on the channel structure, forming a first high-k dielectric layer on the interfacial layer, forming dipoles in the first high-k dielectric layer with a dopant, and forming a second high-k dielectric layer on the first high-k dielectric layer. The dopant includes a first metal element. The second high-k dielectric layer includes a second metal element different from the first metal element.

公开(公告)号：US20240194480A1

公开(公告)日：2024-06-13

申请号：US18581043

申请日：2024-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Ruei JHAN ,  Han-Yu LIN ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L21/02 ,  H01L21/265 ,  H01L21/3105 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L21/02321 ,  H01L21/26586 ,  H01L21/31053 ,  H01L29/401 ,  H01L29/66545

Abstract: A method includes forming a dummy gate structure over a semiconductor substrate, forming a gate spacer over a sidewall of the dummy gate structure, performing a first implantation process to an upper portion of the gate spacer using a first dosage source, and performing a second implantation process to the upper portion of the gate spacer using a second dosage source including carbon. The second dosage source is different from the first dosage source.