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    DEEP TRENCH ISOLATION STRUCTURE FOR IMAGE SENSORS
    21.
    发明申请
    DEEP TRENCH ISOLATION STRUCTURE FOR IMAGE SENSORS 有权
    图像传感器深度分离结构

    公开(公告)号：US20150295005A1

    公开(公告)日：2015-10-15

    申请号：US14253025

    申请日：2014-04-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yuan-Tai Tseng ,  Yu-Hsing Chang ,  Ming Chyi Liu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

    IPC: H01L27/146

    CPC classification number: H01L27/14638 ,  H01L21/76232 ,  H01L27/14607 ,  H01L27/14616 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14643 ,  H01L27/14654 ,  H01L27/14689 ,  H01L27/14692 ,  H01L29/0649

    Abstract: Some embodiments of the present disclosure relate to a deep trench isolation structure. This deep trench isolation structure is formed on a semiconductor substrate having an upper semiconductor surface. A deep trench, which has a deep trench width as measured between opposing deep trench sidewalls, extends into the semiconductor substrate beneath the upper semiconductor surface. A fill material is formed in the deep trench, and a dielectric liner is disposed on a lower surface and sidewalls of the deep trench to separate the fill material from the semiconductor substrate. A shallow trench region has sidewalls that extend upwardly from the sidewalls of the deep trench to the upper semiconductor surface. The shallow trench region has a shallow trench width that is greater than the deep trench width. A dielectric material fills the shallow trench region and extends over top of the conductive material in the deep trench.

    Abstract translation: 本公开的一些实施例涉及深沟槽隔离结构。 该深沟槽隔离结构形成在具有上半导体表面的半导体衬底上。 在相对的深沟槽侧壁之间测量的具有深沟槽宽度的深沟槽延伸到半导体衬底的下半导体表面下方。 填充材料形成在深沟槽中，并且电介质衬垫设置在深沟槽的下表面和侧壁上，以将填充材料与半导体衬底分离。 浅沟槽区域具有从深沟槽的侧壁向上延伸到上半导体表面的侧壁。 浅沟槽区域具有大于深沟槽宽度的浅沟槽宽度。 电介质材料填充浅沟槽区域并在深沟槽中延伸到导电材料的顶部。

    Recessed channel structure in FDSOI
    23.
    发明授权
    Recessed channel structure in FDSOI 有权

    公开(公告)号：US11316026B2

    公开(公告)日：2022-04-26

    申请号：US16420469

    申请日：2019-05-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming Chyi Liu

    IPC: H01L29/423 ,  H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L29/786 ,  H01L29/78

    Abstract: An integrated circuit includes a SOI substrate comprising a base substrate, an insulator layer, and a semiconductor device layer. Source and drain regions in the semiconductor device layer are spaced apart by a channel region in the semiconductor device layer. A gate electrode is disposed over the channel region and has a bottom surface that extends below a top surface of the semiconductor device layer. A sidewall spacer structure extends along outer sidewalls of the gate electrode and has a bottom surface that rests on the top surface of the semiconductor device layer. A gate dielectric separates the channel region from the bottom surface of the gate electrode and contacts the bottom surface of the sidewall spacer structure. The channel region beneath the bottom surface of the gate electrode corresponds to the semiconductor device layer and has a thickness of less than 40 angstroms.

    Cell boundary structure for embedded memory
    25.
    发明授权
    Cell boundary structure for embedded memory 有权

    公开(公告)号：US11296100B2

    公开(公告)日：2022-04-05

    申请号：US16908991

    申请日：2020-06-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming Chyi Liu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yu-Hsing Chang

    IPC: H01L27/11521 ,  H01L21/28 ,  H01L27/11534 ,  H01L27/11548 ,  H01L21/762 ,  H01L27/11526 ,  H01L29/423 ,  H01L23/528

    Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

    HIGH ASPECT RATIO BOSCH DEEP ETCH
    26.
    发明申请
    HIGH ASPECT RATIO BOSCH DEEP ETCH 有权

    公开(公告)号：US20220102155A1

    公开(公告)日：2022-03-31

    申请号：US17032362

    申请日：2020-09-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Hsing Chang ,  Ming Chyi Liu ,  Shih-Chang Liu

    IPC: H01L21/3065 ,  H01L49/02 ,  H01L21/308

    Abstract: In some methods, a first recess is etched in a selected region of a substrate. A first polymer liner is formed on sidewalls and a bottom surface of the first recess. A portion of the first polymer liner is removed from the bottom surface, and a remaining portion of the first polymer liner is left along the sidewalls. The first recess is deepened to establish a second recess while the remaining portion of the first polymer liner is left along the sidewalls. A first oxide liner is formed along the sidewalls and along sidewalls and a bottom surface of the second recess. A portion of the first oxide liner is removed from a bottom surface of the second recess, while a remaining portion of the first oxide liner is left on the sidewalls of the first recess and the sidewalls of the second recess.

    Heater structure with a gas-filled isolation structure to improve thermal efficiency in a modulator device
    27.
    发明授权
    Heater structure with a gas-filled isolation structure to improve thermal efficiency in a modulator device 有权

    公开(公告)号：US11226506B2

    公开(公告)日：2022-01-18

    申请号：US16821160

    申请日：2020-03-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Wei Lin ,  Ming Chyi Liu

    IPC: G02F1/015 ,  G02F1/025 ,  G02F1/225 ,  G02B6/12 ,  G02F1/21

    Abstract: In some embodiments, the present disclosure relates to a modulator device that includes an input terminal configured to receive impingent light. A first waveguide has a first output region and a first input region that is coupled to the input terminal. A second waveguide is optically coupled to the first waveguide and has second input region and a second output region that is coupled to the input terminal. An output terminal coupled to the first output region of the first waveguide and the second output region of the second waveguide is configured to provide outgoing light that is modulated. A heater structure is configured to provide heat to the first waveguide to induce a temperature difference between the first and second waveguides. A gas-filled isolation structure is proximate to the heater structure and is configured to thermally isolate the second waveguide from the heat provided to the first waveguide.

    Double etch stop layer to protect semiconductor device layers from wet chemical etch
    28.
    发明授权
    Double etch stop layer to protect semiconductor device layers from wet chemical etch 有权

    公开(公告)号：US11164844B2

    公开(公告)日：2021-11-02

    申请号：US16568605

    申请日：2019-09-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen Yu Chen ,  Ming Chyi Liu ,  Eugene Chen

    IPC: H01L23/00 ,  H01L33/00 ,  H01L33/62 ,  H01S5/18 ,  H01L25/075

    Abstract: In some embodiments, the present disclosure relates to a method of forming a package assembly. A wet etch stop layer is formed over a frontside of a semiconductor substrate. A sacrificial semiconductor layer is formed over the wet etch stop layer, and a dry etch stop layer is formed over the sacrificial semiconductor layer. A stack of semiconductor device layers may be formed over the dry etch stop layer. A bonding process is performed to bond the stack of semiconductor device layers to a frontside of an integrated circuit die, wherein the frontside of the semiconductor substrate faces the frontside of the integrated circuit die. A wet etching process is performed to remove the semiconductor substrate, and a dry etching process is performed to remove the wet etch stop layer and the sacrificial semiconductor layer.

    CELL BOUNDARY STRUCTURE FOR EMBEDDED MEMORY
    30.
    发明申请
    CELL BOUNDARY STRUCTURE FOR EMBEDDED MEMORY 审中-公开

    公开(公告)号：US20200321345A1

    公开(公告)日：2020-10-08

    申请号：US16908991

    申请日：2020-06-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming Chyi Liu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yu-Hsing Chang

    IPC: H01L27/11521 ,  H01L21/28 ,  H01L27/11534 ,  H01L27/11548 ,  H01L21/762 ,  H01L27/11526 ,  H01L29/423

    Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

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