公开(公告)号：US11233116B2

公开(公告)日：2022-01-25

申请号：US16933062

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Cheng Chen ,  Wei-Li Huang ,  Chien-Chih Kuo ,  Hon-Lin Huang ,  Chin-Yu Ku ,  Chen-Shien Chen

IPC: H01L49/02 ,  H01F41/04 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/532

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The magnetic element has a first edge. The semiconductor device structure also includes an adhesive element between the magnetic element and the semiconductor substrate, and the adhesive element has a second edge. The semiconductor device structure further includes an isolation element extending across the magnetic element. The isolation element partially covers a top surface of the magnetic element and partially covers sidewall surfaces of the magnetic element. The isolation element has a third edge, and the second edge is closer to the third edge than the first edge. In addition, the semiconductor device structure includes a conductive line over the isolation element.

公开(公告)号：US11171085B2

公开(公告)日：2021-11-09

申请号：US16222107

申请日：2018-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hon-Lin Huang ,  Wei-Li Huang ,  Chun-Kai Tzeng ,  Cheng-Jen Lin ,  Chin-Yu Ku

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L23/532

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, and the substrate includes a first region and a second region. The semiconductor device structure includes a first conductive structure formed over the first region of the substrate and a bottom magnetic layer formed over the second region of the substrate. The semiconductor device structure also includes a second conductive structure formed over the bottom magnetic layer and a first insulating layer formed over a sidewall surface of the first conductive structure. The semiconductor device structure further includes a second insulating layer formed over the first insulating layer, and the second insulating layer has a stair-shaped structure.

公开(公告)号：US11127703B2

公开(公告)日：2021-09-21

申请号：US16372437

申请日：2019-04-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yu Ku ,  Cheng-Lung Yang ,  Chen-Shien Chen ,  Hon-Lin Huang ,  Chao-Yi Wang ,  Ching-Hui Chen ,  Chien-Hung Kuo

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L21/78 ,  H01L21/683 ,  H01L23/31

Abstract: Semiconductor devices are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump. The spacer surrounds the bump and disposed between the etching stop layer and the bump.

公开(公告)号：US20200343162A1

公开(公告)日：2020-10-29

申请号：US16925332

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Lung Yang ,  Chih-Hung Su ,  Chen-Shien Chen ,  Hon-Lin Huang ,  Kun-Ming Tsai ,  Wei-Je Lin

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/528 ,  H01L21/48

Abstract: A semiconductor device includes a first conductive layer, an organic layer and a silicon layer. The first conductive layer includes a first surface. The organic layer is disposed over the first surface of the first conductive layer. The silicon layer is disposed over the organic layer and extended onto and in contact with the first surface of the first conductive layer.

公开(公告)号：US10510661B2

公开(公告)日：2019-12-17

申请号：US16203632

申请日：2018-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hon-Lin Huang ,  Chen-Shien Chen ,  Chin-Yu Ku ,  Kuan-Chih Huang ,  Wei-Li Huang

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L23/31

Abstract: Semiconductor devices and methods of forming the same are provided. One of the semiconductor devices comprises a conductive layer, a first dielectric layer disposed over the conductive layer, a magnetic layer disposed over the first dielectric layer, and a plurality of tantalum layers and a plurality of tantalum oxide layers alternately disposed between the magnetic layer and the first dielectric layer.

公开(公告)号：US20190229081A1

公开(公告)日：2019-07-25

申请号：US16372437

申请日：2019-04-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yu Ku ,  Cheng-Lung Yang ,  Chen-Shien Chen ,  Hon-Lin Huang ,  Chao-Yi Wang ,  Ching-Hui Chen ,  Chien-Hung Kuo

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/78

Abstract: Semiconductor devices are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump. The spacer surrounds the bump and disposed between the etching stop layer and the bump.

公开(公告)号：US10276561B2

公开(公告)日：2019-04-30

申请号：US15714226

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Tseng Chen ,  Hon-Lin Huang ,  Chun-Hsien Huang ,  Yu-Hung Lin

IPC: H01L27/06 ,  H01L21/8234 ,  H01L21/02 ,  H01L49/02

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes transferring the substrate from a stage to a deposition chamber, and no heating operation is performed on the stage. The method also includes depositing a resistor layer on the substrate. The resistor layer may have a major structure that is amorphous.

公开(公告)号：US10163781B1

公开(公告)日：2018-12-25

申请号：US15798422

申请日：2017-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hon-Lin Huang ,  Chen-Shien Chen ,  Chin-Yu Ku ,  Kuan-Chih Huang ,  Wei-Li Huang

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L23/31

Abstract: Semiconductor devices and methods of forming the same are disclosed. One of the semiconductor devices includes a conductive layer, a first dielectric layer, a magnetic layer and an etch stop stack. The first dielectric layer is disposed over the conductive layer. The magnetic layer is disposed over the first dielectric layer. The etch stop stack is disposed between the magnetic layer and the first dielectric layer. The etch stop stack includes a second dielectric layer and a plurality of unit layers between the second dielectric layer and the magnetic layer, and each of the plurality of unit layers comprises a tantalum layer and a tantalum oxide layer on the tantalum layer.

公开(公告)号：US09287153B2

公开(公告)日：2016-03-15

申请号：US14461035

申请日：2014-08-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Kai Chen ,  Hung-Chih Wang ,  Hon-Lin Huang ,  Shih-Chi Lin

IPC: B05D3/06 ,  H01L21/677 ,  H01L21/67 ,  C30B25/10

CPC classification number: H01L21/67167 ,  C30B25/105 ,  C30B29/06 ,  C30B33/02 ,  C30B35/00 ,  H01L21/67098

Abstract: A semiconductor baking apparatus includes a load lock chamber, a process chamber, a transfer chamber, a first interior door, and a controller. The process chamber has a first accommodating space therein. The transfer chamber has a second accommodating space therein, and the transfer chamber is connected to the load lock chamber and the process chamber. The first interior door is between the process chamber and the transfer chamber. When the first interior door is opened, the first accommodating space is communicated with the second accommodating space. The controller is programmed to open the first interior door when the semiconductor baking apparatus idles.

Abstract translation: 半导体烘烤装置包括负载锁定室，处理室，传送室，第一室内门和控制器。 处理室在其中具有第一容纳空间。 传送室在其中具有第二容纳空间，并且传送室连接到负载锁定室和处理室。 第一内门位于处理室和传送室之间。 当第一内门打开时，第一容纳空间与第二容纳空间连通。 当半导体烘烤设备闲置时，控制器被编程为打开第一内门。

公开(公告)号：US11462425B2

公开(公告)日：2022-10-04

申请号：US16910095

申请日：2020-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Wei Lu ,  Hon-Lin Huang ,  Hung-Chih Wang

IPC: H01L21/67 ,  C23C18/16 ,  B05C11/06 ,  H01L21/673

Abstract: A semiconductor processing station includes first and second chambers, and a cooling stage. The second chamber includes a cooling pipe disposed inside the second chamber, and an external pipe. The cooling pipe includes a first segment disposed along a sidewall of the second chamber, and a second segment disposed perpendicular to the first segment and located above a wafer carrier in the second chamber. An end of the second segment is connected to an end of the first segment. The external pipe is connected to the second segment distal from the end of the second segment to provide a fluid to flow through the cooling pipe from an exterior to an interior of the second chamber. The fluid discharges toward the wafer carrier through the first segment. The first chamber is surrounded by the second chamber and the cooling stage, and communicates between the cooling stage and the second chamber.