公开(公告)号：US11177228B2

公开(公告)日：2021-11-16

申请号：US16436795

申请日：2019-06-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sheng-Yu Wu ,  Ching-Hui Chen ,  Mirng-Ji Lii ,  Kai-Di Wu ,  Chien-Hung Kuo ,  Chao-Yi Wang ,  Hon-Lin Huang ,  Zi-Zhong Wang ,  Chun-Mao Chiu

IPC: H01L23/00

Abstract: A semiconductor device comprises a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump over the conductive pad, a conductive cap over the conductive bump, and a passivation layer over the semiconductor substrate and surrounding the conductive bump. A combination of the conductive bump and the conductive cap has a stepped sidewall profile. The passivation layer has an inner sidewall at least partially facing and spaced apart from an outer sidewall of the conductive bump.

公开(公告)号：US10276528B2

公开(公告)日：2019-04-30

申请号：US15652251

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yu Ku ,  Cheng-Lung Yang ,  Chen-Shien Chen ,  Hon-Lin Huang ,  Chao-Yi Wang ,  Ching-Hui Chen ,  Chien-Hung Kuo

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/78 ,  H01L21/683

Abstract: A semiconductor device and a manufacturing method for the semiconductor device are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump a spacer and surrounds the bump and disposed between the etching stop layer and the bump.

公开(公告)号：US10163842B2

公开(公告)日：2018-12-25

申请号：US15489954

申请日：2017-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Hung Kuo ,  Chin-Yu Ku ,  Yuh-Sen Chang ,  Hon-Lin Huang ,  Sheng-Yu Wu ,  Ching-Hui Chen ,  Mirng-Ji Lii

IPC: H01L33/50 ,  H01L23/00

Abstract: A semiconductor structure includes an interconnect structure, at least one first metal pad, at least one second metal pad, at least one first bump, at least one second bump, at least one photosensitive material, and a bonding layer. The first metal pad and the second metal pad are disposed on and electrically connected to the interconnect structure. The first bump is disposed on the first metal pad. The second bump is disposed on the second metal pad. The photosensitive material is disposed on the first bump. The bonding layer is in contact with the photosensitive material and the second bump. The photosensitive material is disposed between the first bump and the bonding layer.

公开(公告)号：US20200035634A1

公开(公告)日：2020-01-30

申请号：US16594091

申请日：2019-10-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yu Ku ,  Hon-Lin Huang ,  Chao-Yi Wang ,  Chen-Shien Chen ,  Chien-Hung Kuo

IPC: H01L23/00

Abstract: A method of forming a semiconductor device is provided. A first substrate is provided with a conductive feature therein, a metal bump over the conductive feature and a passivation stack aside the metal bump. A first insulating layer is formed over the metal bump and the passivation stack. First and second patterning processes are performed to form first and second opening patterns in the first insulating layer. The metal bump is exposed by the second patterning process. A second substrate is provided with a second insulating layer thereon. The second substrate is bonded to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer. The first insulating layer and a portion of the passivation stack are removed.

公开(公告)号：US20190326239A1

公开(公告)日：2019-10-24

申请号：US15957919

申请日：2018-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yu Ku ,  Hon-Lin Huang ,  Chao-Yi Wang ,  Chen-Shien Chen ,  Chien-Hung Kuo

IPC: H01L23/00

Abstract: A method of forming a semiconductor device is provided. A first substrate is provided with a conductive feature therein, a metal bump over the conductive feature and a passivation stack aside the metal bump. A first insulating layer is formed over the metal bump and the passivation stack. First and second patterning processes are performed to form first and second opening patterns in the first insulating layer. The metal bump is exposed by the second patterning process. A second substrate is provided with a second insulating layer thereon. The second substrate is bonded to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer. The first insulating layer and a portion of the passivation stack are removed.

公开(公告)号：US11127703B2

公开(公告)日：2021-09-21

申请号：US16372437

申请日：2019-04-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yu Ku ,  Cheng-Lung Yang ,  Chen-Shien Chen ,  Hon-Lin Huang ,  Chao-Yi Wang ,  Ching-Hui Chen ,  Chien-Hung Kuo

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L21/78 ,  H01L21/683 ,  H01L23/31

Abstract: Semiconductor devices are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump. The spacer surrounds the bump and disposed between the etching stop layer and the bump.

公开(公告)号：US20190229081A1

公开(公告)日：2019-07-25

申请号：US16372437

申请日：2019-04-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yu Ku ,  Cheng-Lung Yang ,  Chen-Shien Chen ,  Hon-Lin Huang ,  Chao-Yi Wang ,  Ching-Hui Chen ,  Chien-Hung Kuo

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/78

Abstract: Semiconductor devices are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump. The spacer surrounds the bump and disposed between the etching stop layer and the bump.

公开(公告)号：US11081459B2

公开(公告)日：2021-08-03

申请号：US16594091

申请日：2019-10-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yu Ku ,  Hon-Lin Huang ,  Chao-Yi Wang ,  Chen-Shien Chen ,  Chien-Hung Kuo

IPC: H01L23/00

Abstract: A method of forming a semiconductor device is provided. A first substrate is provided with a conductive feature therein, a metal bump over the conductive feature and a passivation stack aside the metal bump. A first insulating layer is formed over the metal bump and the passivation stack. First and second patterning processes are performed to form first and second opening patterns in the first insulating layer. The metal bump is exposed by the second patterning process. A second substrate is provided with a second insulating layer thereon. The second substrate is bonded to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer. The first insulating layer and a portion of the passivation stack are removed.

公开(公告)号：US10483226B2

公开(公告)日：2019-11-19

申请号：US15957919

申请日：2018-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yu Ku ,  Hon-Lin Huang ,  Chao-Yi Wang ,  Chen-Shien Chen ,  Chien-Hung Kuo

IPC: H01L23/00

Abstract: A method of forming a semiconductor device is provided. A first substrate is provided with a conductive feature therein, a metal bump over the conductive feature and a passivation stack aside the metal bump. A first insulating layer is formed over the metal bump and the passivation stack. First and second patterning processes are performed to form first and second opening patterns in the first insulating layer. The metal bump is exposed by the second patterning process. A second substrate is provided with a second insulating layer thereon. The second substrate is bonded to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer. The first insulating layer and a portion of the passivation stack are removed.

公开(公告)号：US10319695B2

公开(公告)日：2019-06-11

申请号：US15715659

申请日：2017-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sheng-Yu Wu ,  Ching-Hui Chen ,  Mirng-Ji Lii ,  Kai-Di Wu ,  Chien-Hung Kuo ,  Chao-Yi Wang ,  Hon-Lin Huang ,  Zi-Zhong Wang ,  Chun-Mao Chiu

IPC: H01L23/00

Abstract: A semiconductor device includes a semiconductor substrate. A pad region is disposed on the semiconductor substrate. A micro bump is disposed on the pad region. The micro bump has a first portion on the pad region and a second portion on the first portion. The first portion and the second portion have different widths. The first portion has a first width and the second portion has a second width. The first width is larger or smaller than the second width. The micro bump includes nickel and gold. The semiconductor device also includes a passivation layer overlying a portion of the pad region.