公开(公告)号：US11557508B2

公开(公告)日：2023-01-17

申请号：US16994091

申请日：2020-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Wei-Li Huang ,  Sheng-Pin Yang ,  Chi-Cheng Chen ,  Hon-Lin Huang ,  Chin-Yu Ku ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L23/04 ,  H01L23/522 ,  H01L49/02 ,  H01F41/04 ,  H01F17/00 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first conductive line over a substrate. The semiconductor device structure includes a first protection cap over the first conductive line. The semiconductor device structure includes a first photosensitive dielectric layer over the substrate, the first conductive line, and the first protection cap. The semiconductor device structure includes a conductive via structure passing through the first photosensitive dielectric layer and connected to the first protection cap. The semiconductor device structure includes a second conductive line over the conductive via structure and the first photosensitive dielectric layer. The semiconductor device structure includes a second protection cap over the second conductive line. The semiconductor device structure includes a second photosensitive dielectric layer over the first photosensitive dielectric layer, the second conductive line, and the second protection cap.

公开(公告)号：US11177228B2

公开(公告)日：2021-11-16

申请号：US16436795

申请日：2019-06-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sheng-Yu Wu ,  Ching-Hui Chen ,  Mirng-Ji Lii ,  Kai-Di Wu ,  Chien-Hung Kuo ,  Chao-Yi Wang ,  Hon-Lin Huang ,  Zi-Zhong Wang ,  Chun-Mao Chiu

IPC: H01L23/00

Abstract: A semiconductor device comprises a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump over the conductive pad, a conductive cap over the conductive bump, and a passivation layer over the semiconductor substrate and surrounding the conductive bump. A combination of the conductive bump and the conductive cap has a stepped sidewall profile. The passivation layer has an inner sidewall at least partially facing and spaced apart from an outer sidewall of the conductive bump.

公开(公告)号：US20200321230A1

公开(公告)日：2020-10-08

申请号：US16910095

申请日：2020-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Wei Lu ,  Hon-Lin Huang ,  Hung-Chih Wang

IPC: H01L21/67 ,  C23C18/16 ,  B05C11/06 ,  H01L21/673

Abstract: A semiconductor processing station includes first and second chambers, and a cooling stage. The second chamber includes a cooling pipe disposed inside the second chamber, and an external pipe. The cooling pipe includes a first segment disposed along a sidewall of the second chamber, and a second segment disposed perpendicular to the first segment and located above a wafer carrier in the second chamber. An end of the second segment is connected to an end of the first segment. The external pipe is connected to the second segment distal from the end of the second segment to provide a fluid to flow through the cooling pipe from an exterior to an interior of the second chamber. The fluid discharges toward the wafer carrier through the first segment. The first chamber is surrounded by the second chamber and the cooling stage, and communicates between the cooling stage and the second chamber.

公开(公告)号：US10276528B2

公开(公告)日：2019-04-30

申请号：US15652251

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yu Ku ,  Cheng-Lung Yang ,  Chen-Shien Chen ,  Hon-Lin Huang ,  Chao-Yi Wang ,  Ching-Hui Chen ,  Chien-Hung Kuo

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/78 ,  H01L21/683

Abstract: A semiconductor device and a manufacturing method for the semiconductor device are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump a spacer and surrounds the bump and disposed between the etching stop layer and the bump.

公开(公告)号：US10163842B2

公开(公告)日：2018-12-25

申请号：US15489954

申请日：2017-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Hung Kuo ,  Chin-Yu Ku ,  Yuh-Sen Chang ,  Hon-Lin Huang ,  Sheng-Yu Wu ,  Ching-Hui Chen ,  Mirng-Ji Lii

IPC: H01L33/50 ,  H01L23/00

Abstract: A semiconductor structure includes an interconnect structure, at least one first metal pad, at least one second metal pad, at least one first bump, at least one second bump, at least one photosensitive material, and a bonding layer. The first metal pad and the second metal pad are disposed on and electrically connected to the interconnect structure. The first bump is disposed on the first metal pad. The second bump is disposed on the second metal pad. The photosensitive material is disposed on the first bump. The bonding layer is in contact with the photosensitive material and the second bump. The photosensitive material is disposed between the first bump and the bonding layer.

公开(公告)号：US20170221737A1

公开(公告)日：2017-08-03

申请号：US15009833

申请日：2016-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Wei Lu ,  Hon-Lin Huang ,  Hung-Chih Wang

IPC: H01L21/67 ,  H01L21/677

CPC classification number: H01L21/67196 ,  B05C11/06 ,  C23C18/1691 ,  H01L21/67109 ,  H01L21/67201 ,  H01L21/67303

Abstract: A chamber includes a sidewall, a cooling pipe, and an external pipe. The cooling pipe includes a first segment extending along the sidewall of the chamber, and includes multiple purge nozzles. The external pipe extends to inside the chamber and is connected to the first segment of the cooling pipe. A semiconductor processing station includes a central transfer chamber, a load lock chamber, and a cooling stage. The load lock chamber and the cooling stage are disposed adjacent to the central transfer chamber. The load lock chamber is adapted to contain a wafer carrier having multiple wafers. The central transfer chamber communicates between the cooling stage and the load lock chamber to transfer a wafer between the cooling stage and the load lock chamber. A semiconductor process using the semiconductor processing station is also provided.

公开(公告)号：US10720487B2

公开(公告)日：2020-07-21

申请号：US16260439

申请日：2019-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yu Ku ,  Chi-Cheng Chen ,  Hon-Lin Huang ,  Wei-Li Huang ,  Chun-Yi Wu ,  Chen-Shien Chen

IPC: H01L49/02

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming an etch stop layer over a semiconductor substrate and forming a magnetic element over the etch stop layer. The method also includes forming an isolation element extending across the magnetic element. The isolation element partially covers the top surface of the magnetic element and partially covers sidewall surfaces of the magnetic element. The method further includes forming a conductive line over the isolation element. In addition, the method includes forming a dielectric layer over the conductive line, the isolation element, and the magnetic element.

公开(公告)号：US20200035634A1

公开(公告)日：2020-01-30

申请号：US16594091

申请日：2019-10-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yu Ku ,  Hon-Lin Huang ,  Chao-Yi Wang ,  Chen-Shien Chen ,  Chien-Hung Kuo

IPC: H01L23/00

Abstract: A method of forming a semiconductor device is provided. A first substrate is provided with a conductive feature therein, a metal bump over the conductive feature and a passivation stack aside the metal bump. A first insulating layer is formed over the metal bump and the passivation stack. First and second patterning processes are performed to form first and second opening patterns in the first insulating layer. The metal bump is exposed by the second patterning process. A second substrate is provided with a second insulating layer thereon. The second substrate is bonded to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer. The first insulating layer and a portion of the passivation stack are removed.

公开(公告)号：US20190326239A1

公开(公告)日：2019-10-24

申请号：US15957919

申请日：2018-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yu Ku ,  Hon-Lin Huang ,  Chao-Yi Wang ,  Chen-Shien Chen ,  Chien-Hung Kuo

IPC: H01L23/00

Abstract: A method of forming a semiconductor device is provided. A first substrate is provided with a conductive feature therein, a metal bump over the conductive feature and a passivation stack aside the metal bump. A first insulating layer is formed over the metal bump and the passivation stack. First and second patterning processes are performed to form first and second opening patterns in the first insulating layer. The metal bump is exposed by the second patterning process. A second substrate is provided with a second insulating layer thereon. The second substrate is bonded to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer. The first insulating layer and a portion of the passivation stack are removed.

公开(公告)号：US20190295925A1

公开(公告)日：2019-09-26

申请号：US15933396

申请日：2018-03-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Lung Yang ,  CHIH-HUNG Su ,  Chen-Shien Chen ,  Hon-Lin Huang ,  Kun-Ming Tsai ,  Wei-Je Lin

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/528 ,  H01L21/48

Abstract: Semiconductor devices and methods of forming the same are disclosed. One of the semiconductor devices includes a first conductive layer, an organic layer, a silicon layer, a magnetic layer and a second conductive layer. The organic layer is disposed over and exposes a portion of the first conductive layer. The silicon layer is disposed on and in contact with the organic layer. The magnetic layer is disposed over the first conductive layer. The second conductive layer is disposed over the organic layer and the magnetic layer to electrically connect the first conductive layer.