公开(公告)号：US09773779B2

公开(公告)日：2017-09-26

申请号：US14856813

申请日：2015-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： I-Tseng Chen ,  Hon-Lin Huang ,  Chun-Hsien Huang ,  Yu-Hung Lin

IPC: H01L21/20 ,  H01L27/06 ,  H01L21/8234 ,  H01L21/02 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L21/02271 ,  H01L21/823437 ,  H01L28/20

Abstract: A semiconductor device structure including a resistor layer is provided. The semiconductor device structure includes a gate structure formed over the first region of the substrate and an inter-layer dielectric (ILD) layer formed adjacent to the gate structure. The semiconductor device structure further includes a resistor layer is formed over the ILD layer over the second region of the substrate, and the major structure of the resistor layer is amorphous.

公开(公告)号：US20180026031A1

公开(公告)日：2018-01-25

申请号：US15714226

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Tseng Chen ,  Hon-Lin Huang ,  Chun-Hsien Huang ,  Yu-Hung Lin

IPC: H01L27/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L21/02271 ,  H01L21/823437 ,  H01L28/20

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes transferring the substrate from a stage to a deposition chamber, and no heating operation is performed on the stage. The method also includes depositing a resistor layer on the substrate. The resistor layer may have a major structure that is amorphous.

公开(公告)号：US10276561B2

公开(公告)日：2019-04-30

申请号：US15714226

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Tseng Chen ,  Hon-Lin Huang ,  Chun-Hsien Huang ,  Yu-Hung Lin

IPC: H01L27/06 ,  H01L21/8234 ,  H01L21/02 ,  H01L49/02

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes transferring the substrate from a stage to a deposition chamber, and no heating operation is performed on the stage. The method also includes depositing a resistor layer on the substrate. The resistor layer may have a major structure that is amorphous.

公开(公告)号：US09793204B2

公开(公告)日：2017-10-17

申请号：US15065800

申请日：2016-03-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Hung Lin ,  Chun-Hsien Huang ,  I-Tseng Chen

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/311 ,  H01L21/027 ,  H01L21/033 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor structure including a conductive structure, a dielectric layer, and a plurality of conductive features is disclosed. The dielectric layer is formed on the conductive structure. A plurality of through holes is formed in the dielectric layer using a metal hard mask, and at least one of the through holes exposes the conductive structure. The conductive features are formed in the through holes. At least one of the conductive features has a bottom surface and at least one sidewall. The bottom surface and the sidewall of the conductive feature intersect to form an interior angle. The interior angles of adjacent two of the conductive features have a difference less than or substantially equal to about 3 degrees.