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    Interconnect strucutre with protective etch-stop
    24.
    发明授权
    Interconnect strucutre with protective etch-stop 有权

    公开(公告)号：US11355390B2

    公开(公告)日：2022-06-07

    申请号：US16876465

    申请日：2020-05-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shao-Kuan Lee ,  Hai-Ching Chen ,  Hsin-Yen Huang ,  Shau-Lin Shue ,  Cheng-Chin Lee

    IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532

    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.

    Selective deposition of barrier layer
    25.
    发明授权
    Selective deposition of barrier layer 有权

    公开(公告)号：US11251073B2

    公开(公告)日：2022-02-15

    申请号：US16837968

    申请日：2020-04-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsin-Yen Huang ,  Hai-Ching Chen ,  Shau-Lin Shue

    IPC: H01L21/786 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311 ,  H01L21/306

    Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece.

    CAPPING LAYER OVERLYING DIELECTRIC STRUCTURE TO INCREASE RELIABILITY
    26.
    发明申请
    CAPPING LAYER OVERLYING DIELECTRIC STRUCTURE TO INCREASE RELIABILITY 有权

    公开(公告)号：US20210193566A1

    公开(公告)日：2021-06-24

    申请号：US16885378

    申请日：2020-05-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ting-Ya Lo ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Hsin-Yen Huang ,  Shau-Lin Shue ,  Shao-Kuan Lee ,  Cheng-Chin Lee

    IPC: H01L23/522 ,  H01L23/538 ,  H01L21/768

    Abstract: Some embodiments relate to a semiconductor structure including an inter-level dielectric (ILD) layer overlying a substrate. A conductive via is disposed within the ILD layer. A plurality of conductive wires overlie the ILD layer. The plurality of conductive wires includes a first conductive wire laterally offset a second conductive wire. A dielectric structure is disposed laterally between the first and second conductive wires. The dielectric structure includes a first dielectric liner, a dielectric layer, and an air-gap. The air-gap is disposed between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is disposed along an upper surface of the dielectric structure. The dielectric capping layer continuously extends between opposing sidewalls of the dielectric structure and is laterally offset from the plurality of conductive wires.

    Semiconductor device structure
    30.
    发明授权
    Semiconductor device structure 有权

    公开(公告)号：US10090245B2

    公开(公告)日：2018-10-02

    申请号：US15728762

    申请日：2017-10-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kai-Fang Cheng ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Hsin-Yen Huang ,  Tien-I Bao ,  Jung-Hsun Tsai

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate and the first conductive structure. The semiconductor device structure includes a second conductive structure over the first conductive structure and extending into the first dielectric layer. The second conductive structure is electrically connected to the first conductive structure. The semiconductor device structure includes a cover layer between the second conductive structure and the first dielectric layer. The cover layer surrounds the second conductive structure, the second conductive structure passes through the cover layer and is partially between the cover layer and the first conductive structure, and the cover layer includes a metal oxide.

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