公开(公告)号：US20160064401A1

公开(公告)日：2016-03-03

申请号：US14468410

申请日：2014-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Min ,  Tsung-Hsueh Yang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/28 ,  H01L21/033 ,  H01L21/311 ,  H01L29/792 ,  H01L29/423

CPC classification number: H01L27/11568 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/26513 ,  H01L21/28282 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/32139 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. A semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.

Abstract translation: 提供了具有非对称轮廓的硬掩模的分裂栅极闪存单元器件的半导体结构。 半导体结构的半导体衬底包括第一源极/漏极区域和第二源极/漏极区域。 半导体结构的控制栅极和存储栅极在第一和第二源/漏区之间的半导体衬底上间隔开。 半导体结构的电荷捕获电介质结构被布置在存储器栅极的相邻侧壁和控制栅极之间，并且布置在存储器栅极下方。 半导体结构的硬掩模布置在控制栅极上并且包括不对称轮廓。 不对称轮廓在远离记忆门的高度逐渐变细。 还提供了一种用于制造具有不对称轮廓的硬掩模的一对分裂栅极闪存单元器件的方法。

公开(公告)号：US11532785B2

公开(公告)日：2022-12-20

申请号：US17074843

申请日：2020-10-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Min ,  Chang-Chih Huang ,  Yuan-Tai Tseng ,  Kuo-Chyuan Tzeng ,  Yihuei Zhu

IPC: H01L45/00 ,  H01L27/24

Abstract: Some embodiments relate to a memory device. The memory device includes a first electrode overlying a substrate. A data storage layer overlies the first electrode. A second electrode overlies the data storage layer. A conductive bridge is selectively formable within the data storage layer to couple the first electrode to the second electrode. An active metal layer is disposed between the data storage layer and the second electrode. A buffer layer is disposed between the active metal layer and the second electrode. The buffer layer has a lower reactivity to oxygen than the active metal layer.

公开(公告)号：US11088202B2

公开(公告)日：2021-08-10

申请号：US16579757

申请日：2019-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Chung-Chiang Min ,  Shih-Chang Liu

IPC: H01L29/82 ,  H01L21/00 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a dielectric structure over a substrate. The integrated chip further includes a memory device having a data storage structure disposed between a bottom electrode and a top electrode. The bottom electrode is electrically coupled to the plurality of lower interconnect layers. A sidewall spacer continuously extends from an outermost sidewall of the data storage structure to below an outermost sidewall of the bottom electrode.

公开(公告)号：US20210091139A1

公开(公告)日：2021-03-25

申请号：US16579757

申请日：2019-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Chung-Chiang Min ,  Shih-Chang Liu

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a dielectric structure over a substrate. The integrated chip further includes a memory device having a data storage structure disposed between a bottom electrode and a top electrode. The bottom electrode is electrically coupled to the plurality of lower interconnect layers. A sidewall spacer continuously extends from an outermost sidewall of the data storage structure to below an outermost sidewall of the bottom electrode.

公开(公告)号：US09711508B2

公开(公告)日：2017-07-18

申请号：US14632569

申请日：2015-02-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Hsueh Yang ,  Chung-Chiang Min ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10808 ,  H01L27/10852 ,  H01L28/90

Abstract: A capacitor structure includes a deep trench, a contact plug, a spacer and a metal-insulator-metal film. The deep trench extends into a crown oxide substrate, and the contact plug is disposed entirely below the crown oxide substrate. The spacer lines the deep trench, and the metal-insulator-metal film is disposed in the deep trench.

公开(公告)号：US09536969B2

公开(公告)日：2017-01-03

申请号：US14493568

申请日：2014-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsueh Yang ,  Chung-Chiang Min ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/792 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L29/42344 ,  H01L27/1157 ,  H01L29/792

Abstract: The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has cuboid shaped memory gate and select gate covered upper surfaces by some spacers. Thus the memory gate and select gate are protected from silicide. The memory gate and select gate are defined self-aligned by the said spacers. The memory gate and select gate are formed by etching back corresponding conductive materials not covered by the spacers instead of recess processes. Thus the memory gate and select gate have planar upper surfaces and are well defined. The disclosed device and method is also capable of further scaling since photolithography processes are reduced.

Abstract translation: 本公开涉及自对准分离门存储器单元及其相关方法。 自对准分离栅极存储单元具有立方形形状的存储栅极，并且通过一些间隔物选择栅极覆盖的上表面。 因此，存储器栅极和选择栅极被保护以防止硅化物。 存储器栅极和选择栅极被所述间隔物自对准地限定。 存储栅极和选择栅极通过蚀刻不被间隔物覆盖的相应导电材料而不是凹陷工艺而形成。 因此，存储器栅极和选择栅极具有平坦的上表面并且被明确定义。 所公开的装置和方法还能够进一步缩放，因为光刻工艺被减少。