公开(公告)号：US12124163B2

公开(公告)日：2024-10-22

申请号：US18359954

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ta Lu ,  Chih-Chiang Tu ,  Cheng-Ming Lin ,  Ching-Yueh Chen ,  Wei-Chung Hu ,  Ting-Chang Hsu ,  Yu-Tung Chen

IPC: G03F1/24 ,  G03F1/36 ,  G03F1/38 ,  G03F1/54 ,  G03F1/64 ,  G03F7/20

CPC classification number: G03F1/24 ,  G03F1/36 ,  G03F1/38 ,  G03F1/54 ,  G03F1/64 ,  G03F7/2004

Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.

公开(公告)号：US11860530B2

公开(公告)日：2024-01-02

申请号：US17809979

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ta Lu ,  Chih-Chiang Tu ,  Cheng-Ming Lin ,  Ching-Yueh Chen ,  Wei-Chung Hu ,  Ting-Chang Hsu ,  Yu-Tung Chen

IPC: G03F1/24 ,  G03F1/54 ,  G03F1/36 ,  G03F1/64 ,  G03F1/38 ,  G03F7/20

CPC classification number: G03F1/24 ,  G03F1/36 ,  G03F1/38 ,  G03F1/54 ,  G03F1/64 ,  G03F7/2004

Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.

公开(公告)号：US10978567B2

公开(公告)日：2021-04-13

申请号：US16573498

申请日：2019-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Chi On Chui ,  Huang-Lin Chao

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L27/088

Abstract: The present disclosure describes a method that can eliminate or minimize the formation of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the method includes providing a substrate with fins thereon; depositing an interfacial layer on the fins; depositing a ferroelectric layer on the interfacial layer; depositing a metal gate layer on the ferroelectric layer; exposing the metal gate layer to a metal-halide gas; and performing a post metallization annealing, where the exposing the metal gate layer to the metal-halide gas and the performing the post metallization annealing occur without a vacuum break.

公开(公告)号：US20210036127A1

公开(公告)日：2021-02-04

申请号：US16526650

申请日：2019-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING , CO., LTD.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Chi-On Chui ,  Ziwei Fang

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/51

Abstract: A method for forming a semiconductor structure is provided. The method includes patterning a semiconductor substrate to form a semiconductor fin, forming a source/drain structure on the semiconductor fin, forming an interfacial layer on the semiconductor fin, treating the interfacial layer with fluorine, forming a ferroelectric gate dielectric layer on the interfacial layer, treating the ferroelectric gate dielectric layer with fluorine, and forming a gate electrode layer on the ferroelectric gate dielectric layer.

公开(公告)号：US10908494B2

公开(公告)日：2021-02-02

申请号：US15687541

申请日：2017-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Cheng-Hsuen Chiang ,  Chih-Ming Chen ,  Huai-Chih Cheng ,  Hao-Ming Chang ,  Hsao Shih ,  Hsin-Yi Yin

IPC: G03F1/26 ,  G03F1/68 ,  G03F1/76 ,  G03F1/82 ,  G03F7/20

Abstract: A method of manufacturing a photomask includes at least the following steps. First, a phase shift layer and a hard mask layer are formed on a light transmitting substrate. A predetermined mask pattern is split into a first pattern and a second pattern. A series of processes is performed so that the hard mask layer and the phase shift layer have the first pattern and the second pattern. The series of processes includes at least the following steps. First, a first exposure process for transferring the first pattern is performed. Thereafter, a second exposure process for transferring the second pattern is performed. The first exposure process and the second exposure process are executed by different machines.

公开(公告)号：US10459332B2

公开(公告)日：2019-10-29

申请号：US15470933

申请日：2017-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Ming Chang ,  Chih-Ming Chen ,  Cheng-Ming Lin ,  Sheng-Chang Hsu ,  Shao-Chi Wei ,  Hsao Shih ,  Li-Chih Lu

IPC: G03F7/26 ,  G03F1/26 ,  H01L21/027 ,  G03F1/38

Abstract: A method of fabricating a photomask includes providing a mask blank; removing a portion of the resist layer to form a patterned resist layer exposing a portion of the cooling layer; patterning the cooling layer by using the patterned resist layer as an etching mask; patterning the opaque layer; and removing the patterned resist layer and the patterned cooling layer. The mask blank includes a light-transmitting substrate and an opaque layer, a cooling layer, and a resist layer sequentially stacked thereon, wherein the cooling layer has a thermal conductivity ranging between 160 and 5000 and an effective atomic number ranging between 5 and 14.

公开(公告)号：US20180299768A1

公开(公告)日：2018-10-18

申请号：US15486305

申请日：2017-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Chi Wei ,  Cheng-Ming Lin ,  Sheng-Chang Hsu ,  Yu-Hsin Hsu ,  Hao-Ming Chang

IPC: G03F1/64 ,  G03F1/22 ,  G03F1/60 ,  G03F7/20

Abstract: A photo mask assembly including a photo mask, a first adhesive layer adhered with the photo mask, a pellicle frame and a pellicle is provided. The pellicle frame includes a plurality of recesses for accommodating the first adhesive layer. The pellicle frame is adhered with the photo mask through the first adhesive layer accommodated in the plurality of recesses. The pellicle is disposed on the pellicle frame. The pellicle frame is between the pellicle and the first adhesive layer. An optical apparatus including the above-mentioned photo mask assembly is also provided.

公开(公告)号：US20180284601A1

公开(公告)日：2018-10-04

申请号：US15470933

申请日：2017-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Ming Chang ,  Chih-Ming Chen ,  Cheng-Ming Lin ,  Sheng-Chang Hsu ,  Shao-Chi Wei ,  Hsao Shih ,  Li-Chih Lu

IPC: G03F1/76 ,  H01L21/027 ,  G03F1/78 ,  G03F1/26 ,  G03F1/50

CPC classification number: G03F1/26 ,  G03F1/38 ,  H01L21/0274

Abstract: A method of fabricating a photomask includes providing a blank mask; removing a portion of the resist layer to form a patterned resist layer exposing a portion of the cooling layer; patterning the cooling layer by using the patterned resist layer as an etching mask; patterning the opaque layer; and removing the patterned resist layer and the patterned cooling layer. The blank mask includes a light-transmitting substrate and an opaque layer, a cooling layer, and a resist layer sequentially stacked thereon, wherein the cooling layer has a thermal conductivity ranging between 160 and 5000 and an effective atomic number ranging between 5 and 14.

公开(公告)号：US20250006739A1

公开(公告)日：2025-01-02

申请号：US18345467

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Chun-I Wu ,  Tsung-Kai Chiu ,  Wei-Yen Woon ,  Szuya Liao

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775

Abstract: A method of forming a complementary field-effect transistor (CFET) device includes: forming a plurality of channel regions stacked vertically over a fin; forming an isolation structure between a first subset of the plurality of channel regions and a second subset of the plurality of channel regions; forming a gate dielectric material around the plurality of channel regions and the isolation structure; forming a work function material around the gate dielectric material; forming a silicon-containing passivation layer around the work function material; after forming the silicon-containing passivation layer, removing a first portion of the silicon-containing passivation layer disposed around the first subset of the plurality of channel regions and keeping a second portion of the silicon-containing passivation layer disposed around the second subset of the plurality of channel regions; and after removing the first portion of the silicon-containing passivation layer, forming a gate fill material around the plurality of channel regions.

公开(公告)号：US12034058B2

公开(公告)日：2024-07-09

申请号：US18129961

申请日：2023-04-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Chi On Chui ,  Huang-Lin Chao

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/516 ,  H01L21/02356 ,  H01L21/28176 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/785 ,  H01L29/7851

Abstract: The present disclosure describes a device that is protected from the effects of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the device includes a substrate with fins thereon; an interfacial layer on the fins; a crystallized ferroelectric layer on the interfacial layer; and a metal gate layer on the ferroelectric layer.