公开(公告)号：US20220035702A1

公开(公告)日：2022-02-03

申请号：US17449994

申请日：2021-10-05

申请人： Toshiba Memory Corporation

发明人： Kenichiro YOSHII ,  Shinichi KANNO

IPC分类号： G06F11/10 ,  G06F3/06 ,  G06F12/1009

摘要： According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit.
The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.

公开(公告)号：US20210200442A1

公开(公告)日：2021-07-01

申请号：US17203027

申请日：2021-03-16

申请人： TOSHIBA MEMORY CORPORATION

发明人： Shinichi KANNO

IPC分类号： G06F3/06 ,  G06F9/455 ,  G06F12/06 ,  G06F12/02

摘要： A memory system connectable to a host includes a nonvolatile memory and a controller. The controller is configured to generate one or more virtual storage regions each of which is associated with a virtual machine running in the host, using physical memory regions of the nonvolatile memory, maintain a threshold value for each of said one or more virtual storage regions, determine a cumulative amount of data that have been written in each of said one or more virtual storage regions, and restrict writing of data with respect to a virtual storage region for which the cumulative amount exceeds the threshold value.

公开(公告)号：US20210165571A1

公开(公告)日：2021-06-03

申请号：US17154185

申请日：2021-01-21

申请人： TOSHIBA MEMORY CORPORATION

发明人： Shinichi KANNO

IPC分类号： G06F3/06 ,  G06F12/02 ,  H04L9/08

摘要： According to one embodiment, when data is to be written to a first physical storage location that is designated by a first physical address, a memory system encrypts the data with the first physical address and a first encryption key, and writes the encrypted data to the first physical storage location. When the encrypted data is to be copied to a second physical storage location, the memory system decrypts the encrypted data with the first physical address and the first encryption key, and re-encrypts the decrypted data with a second encryption key and a copy destination physical address indicative of the second physical storage location.

公开(公告)号：US20210124531A1

公开(公告)日：2021-04-29

申请号：US17144641

申请日：2021-01-08

申请人： TOSHIBA MEMORY CORPORATION

发明人： Shinichi KANNO

IPC分类号： G06F3/06

摘要： According to one embodiment, a memory system determines a write destination block and a write destination location in the write destination block to which write data is to be written, and notifies a host of an identifier of the write data, a block address of the write destination block, and an offset indicative of the write destination location. The memory system retrieves the write data from a write buffer of the host, and writes the write data to the write destination location. In a case where a read command to designate a physical address of first data is received before a write operation of the first data is finished, the memory system reads the first data from the write buffer of the host.

公开(公告)号：US20210042034A1

公开(公告)日：2021-02-11

申请号：US17083529

申请日：2020-10-29

申请人： Toshiba Memory Corporation

发明人： Hirokuni YANO ,  Shinichi KANNO ,  Toshikatsu HIDA ,  Hidenori MATSUZAKI ,  Kazuya KITSUNAI ,  Shigehiro ASANO

IPC分类号： G06F3/06 ,  G11C11/56 ,  G06F12/02

摘要： A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

公开(公告)号：US20190235787A1

公开(公告)日：2019-08-01

申请号：US16126054

申请日：2018-09-10

申请人： Toshiba Memory Corporation

发明人： Shinichi KANNO ,  Hideki YOSHIDA ,  Naoki ESAKA

IPC分类号： G06F3/06

CPC分类号： G06F3/0656 ,  G06F3/0604 ,  G06F3/0679

摘要： According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writing the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.

公开(公告)号：US20190215015A1

公开(公告)日：2019-07-11

申请号：US16357696

申请日：2019-03-19

申请人： TOSHIBA MEMORY CORPORATION

发明人： Shinichi KANNO ,  Hironori UCHIKAWA

IPC分类号： H03M13/29 ,  G06F11/10 ,  H03M13/35 ,  G11C29/52 ,  G06F13/16 ,  H03M13/00 ,  G06F13/40

CPC分类号： H03M13/2906 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1068 ,  G06F13/1673 ,  G06F13/4068 ,  G11C29/52 ,  H03M13/03 ,  H03M13/29 ,  H03M13/35 ,  H03M13/6561 ,  Y02D10/14 ,  Y02D10/151

摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

公开(公告)号：US20190102086A1

公开(公告)日：2019-04-04

申请号：US16207418

申请日：2018-12-03

申请人： Toshiba Memory Corporation

发明人： Shinichi KANNO

IPC分类号： G06F3/06 ,  G06F12/02

CPC分类号： G06F3/061 ,  G06F3/0625 ,  G06F3/0655 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/0253 ,  G06F2212/1016 ,  G06F2212/7204 ,  G06F2212/7205 ,  G06F2212/7208

摘要： According to one embodiment, a memory system is configured to operate as one of semiconductor storage devices in a storage array. The memory system includes a nonvolatile memory and a controller. The controller executes a write operation of writing data, received from a host, to the nonvolatile memory, and an internal operation for managing the memory system. When starting the internal operation, the controller estimates a value related to an amount of reduction in performance of the write operation due to the start of the internal operation, based on content of the started internal operation, and notifies the host or one or more other semiconductor storage devices of the estimated value.

公开(公告)号：US20190079688A1

公开(公告)日：2019-03-14

申请号：US15915589

申请日：2018-03-08

申请人： Toshiba Memory Corporation

发明人： Takeshi ISHIHARA ,  Shinichi KANNO

IPC分类号： G06F3/06

摘要： According to one embodiment, an information processing device includes a characteristics monitoring unit, a determination unit, and a notification unit. The characteristics monitoring unit monitors characteristics information that indicates at least one of its performance and lifetime with respect to a storage device, and includes input/output characteristics. The determination unit determines, based on monitored characteristics information including the input/output characteristics, whether change instruction for changing characteristics is to be notified to the storage device. The notification unit notifies the storage device of the change instruction when the determination unit determines that the change instruction is to be notified.

公开(公告)号：US20180247947A1

公开(公告)日：2018-08-30

申请号：US15700365

申请日：2017-09-11

申请人： Toshiba Memory Corporation

发明人： Shinichi KANNO

IPC分类号： H01L27/11524 ,  H01L27/105

CPC分类号： H01L27/11524 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0631 ,  G06F3/0652 ,  G06F3/0659 ,  G06F12/06 ,  G06F2212/1016 ,  G06F2212/214 ,  G11C16/16 ,  H01L27/1052

摘要： According to one embodiment, a memory system classifies a plurality of nonvolatile memory dies connected to a plurality of channels, into a plurality of die groups such that each of the plurality of nonvolatile memory dies belongs to only one die group. The memory system performs a data write/read operation for one die group of the plurality of die groups in accordance with an I/O command from a host designating one of a plurality of regions including at least one region corresponding to each die group. The memory system manages a group of free blocks in the nonvolatile memory for each of the plurality of die group by using a plurality of free block pools corresponding to the plurality of die groups.