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公开(公告)号：US20250021120A9
公开(公告)日：2025-01-16
申请号：US17877115
申请日：2022-07-29
Inventor： Zheng-Jun Lin , Chung-Cheng Chou , Yu-Der Chih , Chin-I Su
Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.
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公开(公告)号：US20240257870A1
公开(公告)日：2024-08-01
申请号：US18630241
申请日：2024-04-09
Inventor： Zheng-Jun Lin , Chung-Cheng Chou , Yu-Der Chih , Pei-Ling Tseng
IPC: G11C13/00
CPC classification number: G11C13/0064 , G11C13/003 , G11C13/004
Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.
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公开(公告)号：US11715518B2
公开(公告)日：2023-08-01
申请号：US17470849
申请日：2021-09-09
Inventor： Zheng-Jun Lin , Chin-I Su , Pei-Ling Tseng , Chung-Cheng Chou
IPC: G11C13/00
CPC classification number: G11C13/0028 , G11C13/003 , G11C13/0026 , G11C13/0038 , G11C13/0069 , G11C2213/79
Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.
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公开(公告)号：US20230065104A1
公开(公告)日：2023-03-02
申请号：US17981977
申请日：2022-11-07
Inventor： Zheng-Jun Lin , Chung-Cheng Chou , Yu-Der Chih , Pei-Ling Tseng
IPC: G11C13/00
Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.
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公开(公告)号：US20220359008A1
公开(公告)日：2022-11-10
申请号：US17825566
申请日：2022-05-26
Inventor： Zheng-Jun Lin , Chung-Cheng Chou , Pei-Ling Tseng
Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell. A precharger is configured to selectively precharge the sensing circuit to a predetermined precharge voltage
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Patent Agency Ranking
公开(公告)号：US11348638B2
公开(公告)日：2022-05-31
申请号：US17000980
申请日：2020-08-24
Inventor： Zheng-Jun Lin , Chung-Cheng Chou , Pei-Ling Tseng
Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell. A precharger is configured to selectively precharge the sensing circuit to a predetermined precharge voltage.
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公开(公告)号：US20210241830A1
公开(公告)日：2021-08-05
申请号：US17106725
申请日：2020-11-30
Inventor： Zheng-Jun Lin , Chung-Cheng Chou , Yu-Der Chih , Pei-Ling Tseng
IPC: G11C13/00
Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.
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公开(公告)号：US20190287612A1
公开(公告)日：2019-09-19
申请号：US16273608
申请日：2019-02-12
Inventor： Zheng-Jun Lin , Chung-Cheng Chou , Pei-Ling Tseng
Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell. A precharger is configured to selectively precharge the sensing circuit to a predetermined precharge voltage
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公开(公告)号：US12259783B2
公开(公告)日：2025-03-25
申请号：US18183679
申请日：2023-03-14
Inventor： Zheng-Jun Lin , Pei-Ling Tseng , Hsueh-Chih Yang , Chung-Cheng Chou , Yu-Der Chih
Abstract: A semiconductor device includes an error correction code circuit and a register circuit. The error correction code circuit is configured to generate first data according to second data. The register circuit is configured to generate reset information according to a difference between the first data and the second data, for adjusting a memory cell associated with the second data. A method is also disclosed herein.
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公开(公告)号：US12230323B2
公开(公告)日：2025-02-18
申请号：US18304297
申请日：2023-04-20
Inventor： Chin-I Su , Chung-Cheng Chou , Yu-Der Chih , Zheng-Jun Lin
IPC: G11C13/00
Abstract: A memory circuit includes a first driver circuit, a memory cell array including a first column of memory cells, a first transistor coupled between the first driver circuit and the memory cell array, a second driver circuit, a first column of tracking cells and a header circuit coupled to the first driver circuit and the second driver circuit. The first transistor is configured to receive a first select signal. The first column of tracking cells is configured to track a leakage current of the first column of memory cells, and is coupled between a first conductive line and a second conductive line, the first conductive line being coupled to the second driver circuit.
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