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    MEMORY DEVICE AND METHODS
    24.
    发明公开
    MEMORY DEVICE AND METHODS 审中-公开

    公开(公告)号：US20240331786A1

    公开(公告)日：2024-10-03

    申请号：US18741021

    申请日：2024-06-12

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Meng-Sheng CHANG ,  Yao-Jen YANG

    IPC: G11C17/18 ,  G11C17/16 ,  H10B20/20

    CPC classification number: G11C17/18 ,  G11C17/16 ,  H10B20/20

    Abstract: A memory device includes a bit line, a source line, a program word line, a read word line, a memory cell including a program transistor and a read transistor, and a controller. The program transistor includes a gate terminal coupled to the program word line, a first terminal coupled to the source line, and a second terminal. The read transistor includes a gate terminal coupled to the read word line, a first terminal coupled to the bit line, and a second terminal coupled to the second terminal of the program transistor. The controller is configured to, in a programming operation, cause a program current to flow through the memory cell along a first current path. The controller is further configured to, in a read operation, cause a read current to flow through the memory cell along a second current path different from the first current path.

    FUSIBLE STRUCTURES
    28.
    发明公开
    FUSIBLE STRUCTURES 审中-公开

    公开(公告)号：US20230298995A1

    公开(公告)日：2023-09-21

    申请号：US18322481

    申请日：2023-05-23

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Shao-Ting WU ,  Meng-Sheng CHANG ,  Shao-Yu CHOU ,  Chung-I HUANG

    IPC: H01L23/525 ,  H10B20/20

    CPC classification number: H01L23/5256 ,  H10B20/20 ,  H01L21/32139

    Abstract: A fusible structure includes: a metal line in a first metal layer extending along a first direction; and a first dummy structure disposed proximal to the metal line relative to a second direction, the second direction being perpendicular to the first direction, the first dummy structure being in a second metal layer. Relative to the first direction, the metal line includes first, second and third portions, the second portion being between the first portion and third portion. Relative to a third direction that is perpendicular to the first direction and the second direction, the first portion has a first thickness and the second portion has a second thickness, the first thickness being greater than the second thickness.

    MEMORY DEVICE, INTEGRATED CIRCUIT DEVICE AND METHOD
    29.
    发明申请
    MEMORY DEVICE, INTEGRATED CIRCUIT DEVICE AND METHOD 有权

    公开(公告)号：US20230089590A1

    公开(公告)日：2023-03-23

    申请号：US18053030

    申请日：2022-11-07

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Meng-Sheng CHANG ,  Chia-En HUANG ,  Chien-Ying CHEN

    IPC: G06F30/392 ,  G03F1/70 ,  G06F30/398

    Abstract: A memory device includes a bit line, a word line, a memory cell including a capacitor and a transistor, and a controller. The transistor has a gate terminal coupled to the word line, a first terminal, and a second terminal. The capacitor has a first end coupled to the first terminal of the transistor, a second end coupled to the bit line, and an insulating material between the first end and the second end. The controller, in a programming operation, applies a turn-ON voltage via the word line to the gate terminal of the transistor to turn ON the transistor, and applies a program voltage via the bit line to the second end of the capacitor to apply, while the transistor is turned ON, a predetermined break-down voltage or higher between the first end and the second end of the capacitor to break down the insulating material of the capacitor.

    MEMORY INCLUDING METAL RAILS WITH BALANCED LOADING
    30.
    发明申请
    MEMORY INCLUDING METAL RAILS WITH BALANCED LOADING 有权

    公开(公告)号：US20230062566A1

    公开(公告)日：2023-03-02

    申请号：US17460206

    申请日：2021-08-28

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Meng-Sheng CHANG ,  Chia-En HUANG ,  Yi-Ching LIU ,  Yih WANG

    IPC: G11C13/00

    Abstract: Disclosed herein are related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.

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