公开(公告)号：US20190042461A1

公开(公告)日：2019-02-07

申请号：US15958591

申请日：2018-04-20

申请人： Rupin Vakharwala ,  Amin Firoozshahian ,  Stephen Van Doren ,  Rajesh Sankaran ,  Mahesh Madhav ,  Omid Azizi ,  Andreas Kleen ,  Mahesh Maddury ,  Ashok Raj

发明人： Rupin Vakharwala ,  Amin Firoozshahian ,  Stephen Van Doren ,  Rajesh Sankaran ,  Mahesh Madhav ,  Omid Azizi ,  Andreas Kleen ,  Mahesh Maddury ,  Ashok Raj

IPC分类号： G06F12/1009 ,  G06F3/06 ,  G06F12/0862 ,  G06F9/38

摘要： A processing device includes a core to execute instructions, and memory management circuitry coupled to, memory, the core and an I/O device that supports page faults. The memory management circuitry includes an express invalidations circuitry, and a page translation permission circuitry. The memory management circuitry is to, while the core is executing the instructions, receive a command to pause communication between the I/O device and the memory. In response to receiving the command to pause the communication, modify permissions of page translations by the page translation permission circuitry and transmit an invalidation request, by the express invalidations circuitry to the I/O device, to cause cached page translations in the I/O device to be invalidated.

公开(公告)号：US20070150699A1

公开(公告)日：2007-06-28

申请号：US11321213

申请日：2005-12-28

申请人： Ioannis Schoinas ,  Doddaballapur Jayasimha ,  Eric Delano ,  Allen Baum ,  Akhilesh Kumar ,  Steven Chang ,  Suresh Chittor ,  Kenneth Creta ,  Stephen Van Doren

发明人： Ioannis Schoinas ,  Doddaballapur Jayasimha ,  Eric Delano ,  Allen Baum ,  Akhilesh Kumar ,  Steven Chang ,  Suresh Chittor ,  Kenneth Creta ,  Stephen Van Doren

IPC分类号： G06F15/00

CPC分类号： H04L45/00 ,  H04L45/04

摘要： Methods and apparatuses for firm partitioning of a computing platform.

摘要翻译： 用于计算平台的固定分区的方法和装置。

公开(公告)号：US06961825B2

公开(公告)日：2005-11-01

申请号：US09768418

申请日：2001-01-24

申请人： Simon C. Steely, Jr. ,  Stephen Van Doren ,  Madhumitra Sharma

发明人： Simon C. Steely, Jr. ,  Stephen Van Doren ,  Madhumitra Sharma

IPC分类号： G06F12/08 ,  H04L29/08 ,  G06F12/00

CPC分类号： H04L67/2804 ,  G06F12/0824 ,  G06F12/0826 ,  H04L67/2852 ,  H04L69/329

摘要： A distributed processing system includes a cache coherency mechanism that essentially encodes network routing information into sectored presence bits. The mechanism organizes the sectored presence bits as one or more arbitration masks that system switches decode and use directly to route invalidate messages through one or more higher levels of the system. The lower level or levels of the system use local routing mechanisms, such as local directories, to direct the invalidate messages to the individual processors that are holding the data of interest.

摘要翻译： 分布式处理系统包括高速缓存一致性机制，其基本上将网络路由信息编码为扇区存在位。 该机制将分区存在位组织为一个或多个仲裁掩码，系统交换机直接解码并使用，以通过系统的一个或多个更高级别路由无效消息。 系统的较低级别或级别使用本地路由机制（如本地目录）将无效消息引导到保存感兴趣的数据的各个处理器。

公开(公告)号：US06226709B1

公开(公告)日：2001-05-01

申请号：US08957688

申请日：1997-10-24

申请人： Paul M. Goodwin ,  Stephen Van Doren

发明人： Paul M. Goodwin ,  Stephen Van Doren

IPC分类号： G06F1200

CPC分类号： G11C11/40611 ,  G06F13/1636 ,  G11C11/406

摘要： A memory system has a plurality of interleaved memory ranks that use SDRAMs requiring a periodic refresh, and an arbiter which controls access to the memory ranks and restricts access to a memory rank being refreshed. The memory ranks are interleaved on a memory module. Counting refresh registers on each memory module are associated with the module's memory ranks. The arbiter has its own counting refresh register. At regular intervals, the arbiter broadcasts a refresh signal along with a refresh address to the modules via a transaction bus. The refresh address provided by the arbiter is latched by the refresh registers which then begin counting at a pre-programmed interval. A refresh to a particular memory rank is triggered when a refresh register associated with the memory rank matches a unique identifier assigned to that rank. The arbiter uses its refresh register to identify the memory rank being refreshed, allowing the arbiter to restrict access to that memory rank. As a result, the memory ranks are refreshed sequentially without ongoing control by the arbiter.

摘要翻译： 存储器系统具有使用需要周期性刷新的SDRAM的多个交错存储器级别，以及控制对存储器排序的访问的仲裁器，并且限制对刷新的存储器级别的存取。 存储器排列在存储器模块上交错。 计数每个内存模块上的刷新寄存器与模块的内存等级相关联。 仲裁器有自己的计数刷新寄存器。 定期地，仲裁器通过事务总线向模块广播刷新信号以及刷新地址。 仲裁器提供的刷新地址由刷新寄存器锁存，然后刷新寄存器以预编程间隔开始计数。 当与存储器排列相关联的刷新寄存器与分配给该等级的唯一标识符匹配时，触发特定存储器级别的刷新。 仲裁器使用其刷新寄存器来识别刷新的内存等级，允许仲裁器限制对该内存等级的访问。 因此，内存级别顺序刷新，而不受仲裁器的持续控制。

公开(公告)号：US20190303281A1

公开(公告)日：2019-10-03

申请号：US15941468

申请日：2018-03-30

申请人： Amin Firoozshahian ,  Vedaraman Greetha ,  Andreas Kleen ,  Stephen Van Doren ,  Omid Azizi ,  Mahesh Madhav ,  Mahesh Maddury ,  Chandan Egbert

发明人： Amin Firoozshahian ,  Vedaraman Greetha ,  Andreas Kleen ,  Stephen Van Doren ,  Omid Azizi ,  Mahesh Madhav ,  Mahesh Maddury ,  Chandan Egbert

IPC分类号： G06F12/02 ,  G06F12/06

摘要： Various systems and methods for controlling memory traffic flow rate are described herein. A system for computer memory management, the system comprising: rate control circuitry to: receive a rate exceeded signal from monitoring circuitry, the rate exceeded signal indicating that memory traffic flow from a traffic source exceeds a threshold; receive a distress signal from a memory controller that interfaces with a memory device, the distress signal indicating that the memory device is oversubscribed; and implement throttle circuitry to throttle the memory traffic flow from the traffic source when the rate exceeded signal and the distress signal are both asserted.

公开(公告)号：US20170286337A1

公开(公告)日：2017-10-05

申请号：US15087154

申请日：2016-03-31

申请人： Ren Wang ,  Yipeng Wang ,  Jr-Shian Tsai ,  Andrew Herdrich ,  Tsung-Yuan Tai ,  Niall McDonnell ,  Stephen Van Doren ,  David Sonnier ,  Debra Bernstein ,  Hugh Wilkinson ,  Narender Vangati ,  Stephen Miller ,  Gage Eads ,  Andrew Cunningham ,  Jonathan Kenny ,  Bruce Richardson ,  William Burroughs ,  Joseph Hasting ,  An Yan ,  James Clee ,  Te Ma ,  Jerry Pirog ,  Jamison Whitesell

发明人： Ren Wang ,  Yipeng Wang ,  Jr-Shian Tsai ,  Andrew Herdrich ,  Tsung-Yuan Tai ,  Niall McDonnell ,  Stephen Van Doren ,  David Sonnier ,  Debra Bernstein ,  Hugh Wilkinson ,  Narender Vangati ,  Stephen Miller ,  Gage Eads ,  Andrew Cunningham ,  Jonathan Kenny ,  Bruce Richardson ,  William Burroughs ,  Joseph Hasting ,  An Yan ,  James Clee ,  Te Ma ,  Jerry Pirog ,  Jamison Whitesell

IPC分类号： G06F13/36 ,  G06F13/40 ,  G06F12/10 ,  G06F13/24

CPC分类号： G06F13/36 ,  G06F12/1027 ,  G06F13/24 ,  G06F13/4004 ,  G06F2212/1021 ,  G06F2212/50 ,  G06F2212/68

摘要： Technologies for a distributed hardware queue manager include a compute device having a procesor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.

公开(公告)号：US06249846B1

公开(公告)日：2001-06-19

申请号：US09547163

申请日：2000-04-11

申请人： Stephen Van Doren ,  Rahul Razdan

发明人： Stephen Van Doren ,  Rahul Razdan

IPC分类号： G06F1202

CPC分类号： G06F12/0806 ,  G06F12/0822

摘要： A method and apparatus for preventing system wide data dependent stalls is provided. Requests that reach the top of a probe queue and which target data that is not contained in an attached cache memory, are stalled until the data is filled into the appropriate location in cache memory. Only the associated central processor unit's probe queue is stalled and not the entire system. Accordingly, the present invention allows a system to chain together two or more concurrent operations for the same data block without adversely affecting system performance.

摘要翻译： 提供了一种用于防止系统范围内的数据相关失速的方法和装置。 达到探测队列顶部的请求以及未包含在附加高速缓冲存储器中的目标数据被停止，直到数据被填充到高速缓冲存储器中的适当位置为止。 只有相关联的中央处理器单元的探测队列停滞，而不是整个系统。 因此，本发明允许系统将相同数据块的两个或多个并发操作链接在一起，而不会不利地影响系统性能。

公开(公告)号：US06105108A

公开(公告)日：2000-08-15

申请号：US957509

申请日：1997-10-24

申请人： Simon C. Steely, Jr. ,  Stephen Van Doren

发明人： Simon C. Steely, Jr. ,  Stephen Van Doren

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0811

摘要： A multiprocessor computer system releases a victim data buffer storing victim data, when system control logic determines that a count of the number of probe messages pending at a specified time equals the number of such probe messages that have had an address comparison performed after the specified time. The specified time occurs when a command to write the victim data element to main memory passes a serialization point of the computer system.The address comparison compares a target address of a probe message with addresses of data stored in the victim data buffer and the associated cache of a CPU of the computer system.

摘要翻译： 多系统计算机系统释放存储受害者数据的受害者数据缓冲器，当系统控制逻辑确定在指定时间内等待的探测消息数量的计数等于在指定时间之后进行了地址比较的探测消息的数量 。 当将受害者数据元素写入主存储器的命令通过计算机系统的序列化点时，会发生指定的时间。 地址比较将探测消息的目标地址与存储在受害者数据缓冲器中的数据的地址以及计算机系统的CPU的相关联的缓存进行比较。

公开(公告)号：US6101581A

公开(公告)日：2000-08-08

申请号：US957217

申请日：1997-10-24

申请人： Stephen Van Doren ,  Simon C. Steely, Jr. ,  Robert Eugene Stewart ,  James Bernard Keller

发明人： Stephen Van Doren ,  Simon C. Steely, Jr. ,  Robert Eugene Stewart ,  James Bernard Keller

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0804 ,  G06F12/0831

摘要： In accordance with the present invention, a method and apparatus is provided for maintaining the coherency of victim data from a time when the data is stored in a victim data buffer until a time when the data is written into a main memory. Alternatively, the coherency of the victim data is preserved until a determination is made that pending probe messages do not target the victim data. At that time the victim data buffer can be deallocated.With both arrangements, a central processing unit can release a victim data buffer at a point in time other than when the data that is stored therein is read from the buffer. Thus, the central processor unit can perform the release or deallocation of the buffer when it is most efficient and when no further access to the data is required.

摘要翻译： 根据本发明，提供一种方法和装置，用于在将数据存储在受害者数据缓冲器中直到数据被写入主存储器的时间内时保持受害者数据的一致性。 或者，保留受害者数据的一致性，直到确定未决探测消息不针对受害者数据为止。 当时可以释放受害者的数据缓冲区。 通过这两种布置，中央处理单元可以在从缓冲器读取存储在其中的数据以外的时间点释放受害者数据缓冲器。 因此，当中央处理器单元最有效并且不需要对数据的进一步访问时，中央处理器单元可以执行缓冲器的释放或释放。

公开(公告)号：US6085294A

公开(公告)日：2000-07-04

申请号：US957129

申请日：1997-10-24

申请人： Stephen Van Doren ,  Rahul Razdan

发明人： Stephen Van Doren ,  Rahul Razdan

IPC分类号： G06F12/08

CPC分类号： G06F12/0806 ,  G06F12/0822

摘要： A method and apparatus for preventing system wide data dependent stalls is provided. Requests that reach the top of a probe queue and which target data that is not contained in an attached cache memory subsystem, are stalled until the data is filled into the appropriate location in cache memory. Only the associated central processor unit's probe queue is stalled and not the entire system. Accordingly, the present invention allows a system to chain together two or more concurrent operations for the same data block without adversely affecting system performance.

摘要翻译： 提供了一种用于防止系统范围内的数据相关失速的方法和装置。 达到探测队列顶部的请求以及连接的高速缓存存储器子系统中未包含的目标数据的请求将停止，直到数据被填充到缓存中的适当位置。 只有相关联的中央处理器单元的探测队列停滞，而不是整个系统。 因此，本发明允许系统将相同数据块的两个或多个并发操作链接在一起，而不会不利地影响系统性能。