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    General purpose micro-coded accelerator
    21.
    发明申请
    General purpose micro-coded accelerator 审中-公开
    通用微码加速器

    公开(公告)号：US20060107027A1

    公开(公告)日：2006-05-18

    申请号：US10987327

    申请日：2004-11-12

    Applicant: Inching Chen ,  Ernest Tsui

    Inventor： Inching Chen ,  Ernest Tsui

    IPC: G06F9/30

    CPC classification number: G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

    Abstract: A micro-coded accelerator may comprise multiple programmable control units, multiple special function units, a cross-bar switch to connect any of the control units to any one or more of the special function units, and a global memory to facilitate processing by these units. Each control unit may have an array of programmable logic arrays (ARPLAs), each of which may be configured in various ways, a local memory, and a switch circuit to enable the components of the control unit to perform various operations. By configuring the ARPLAs, the control units' internal switch circuitry, and the cross-bar switch, the micro-coded accelerator may be dynamically reconfigured to perform multiple types of operations.

    Abstract translation: 微编码加速器可以包括多个可编程控制单元，多个特殊功能单元，将任何控制单元连接到任何一个或多个特殊功能单元的交叉开关，以及一个全局存储器，以便于这些单元进行处理 。 每个控制单元可以具有可编程逻辑阵列（ARPLA）阵列，每个可编程逻辑阵列（ARPLA）可以以各种方式配置，本地存储器和开关电路，以使得控制单元的组件能够执行各种操作。 通过配置ARPLA，控制单元的内部交换电路和交叉开关，可以动态地重新配置微编码加速器以执行多种类型的操作。

    Processor timing apparatus, systems, and methods
    22.
    发明申请
    Processor timing apparatus, systems, and methods 有权
    处理器计时装置，系统和方法

    公开(公告)号：US20050262370A1

    公开(公告)日：2005-11-24

    申请号：US10848479

    申请日：2004-05-18

    Applicant: Ernest Tsui ,  Inching Chen

    Inventor： Ernest Tsui ,  Inching Chen

    IPC: G06F1/26 ,  G06F1/32

    CPC classification number: G06F1/3203

    Abstract: An apparatus and a system, as well as a method and article, may operate to independently adjust a plurality of processor clocks coupled to a corresponding plurality of networked processors responsive to one or more status indicators to provide scalable performance and power consumption.

    Abstract translation: 响应于一个或多个状态指示符，设备和系统以及方法和文章可以操作以独立地调整耦合到对应的多个联网处理器的多个处理器时钟，以提供可扩展的性能和功耗。

    Method and apparatus for manipulating MPEG video
    26.
    发明授权
    Method and apparatus for manipulating MPEG video 有权
    用于操纵MPEG视频的方法和装置

    公开(公告)号：US08290062B1

    公开(公告)日：2012-10-16

    申请号：US09671957

    申请日：2000-09-27

    Applicant: Inching Chen

    Inventor： Inching Chen

    IPC: H04N7/18

    CPC classification number: H04N19/167 ,  H04N19/172 ,  H04N19/176 ,  H04N19/40 ,  H04N21/234309 ,  H04N21/4307 ,  H04N21/4728

    Abstract: A computer implemented method of manipulating and displaying an MPEG stream is described. In one embodiment of the invention, a computer implemented method comprises defining a spatial location across a series of pictures of an MPEG stream; and for each picture of the series of pictures in the MPEG stream, partially decoding the picture to determine an area of the picture falling within the spatial location.

    Abstract translation: 描述了一种操作和显示MPEG流的计算机实现的方法。 在本发明的一个实施例中，一种计算机实现的方法包括：跨MPEG流的一系列图片定义空间位置; 并且对于MPEG流中的一系列图像的每个图像，部分地解码图像以确定落在空间位置内的图像的区域。

    Processor timing apparatus, systems, and methods
    27.
    发明授权
    Processor timing apparatus, systems, and methods 有权
    处理器计时装置，系统和方法

    公开(公告)号：US07472306B2

    公开(公告)日：2008-12-30

    申请号：US10848479

    申请日：2004-05-18

    Applicant: Ernest Tsui ,  Inching Chen

    Inventor： Ernest Tsui ,  Inching Chen

    IPC: G06F1/10 ,  G06F1/12 ,  G06F1/32

    CPC classification number: G06F1/3203

    Abstract: An apparatus and a system, as well as a method and article, may operate to independently adjust a plurality of processor clocks coupled to a corresponding plurality of networked processors responsive to one or more status indicators to provide scalable performance and power consumption. The status indicators may indicate the status of routers coupled to the processors. Additional apparatus, systems, and methods are disclosed.

    Abstract translation: 响应于一个或多个状态指示符，设备和系统以及方法和文章可以操作以独立地调整耦合到对应的多个联网处理器的多个处理器时钟，以提供可扩展的性能和功耗。 状态指示器可以指示耦合到处理器的路由器的状态。 公开了附加装置，系统和方法。

    Systems and methods for packet multicasting with a multi-read buffer
    29.
    发明申请
    Systems and methods for packet multicasting with a multi-read buffer 审中-公开
    用多读缓冲区分组多播的系统和方法

    公开(公告)号：US20050286534A1

    公开(公告)日：2005-12-29

    申请号：US10880152

    申请日：2004-06-28

    Applicant: Inching Chen ,  Vladimir Pudovkin

    Inventor： Inching Chen ,  Vladimir Pudovkin

    IPC: H04L12/28 ,  H04L12/56

    CPC classification number: H04L49/901 ,  H04L45/16 ,  H04L45/60 ,  H04L47/15 ,  H04L49/90

    Abstract: A multi-read buffer latches a start read address of a read pointer of multicast packet data in response to a multi-read mode signal. The read pointer is incremented during a read of the multicast packet data, and the latched start read address is reloaded to the read pointer after the multicast packet data is read for a subsequent reading of the multicast packet data for a next multicast packet. In some data-processing embodiments, the multi-read buffer may be provided between two or more processors of a multi-processor system. In these embodiments, portions of packet data may be validated and reread from buffer by one of the processors.

    Abstract translation: 响应于多读模式信号，多读缓冲器锁存多播分组数据的读指针的开始读地址。 读取指针在读取多播分组数据期间递增，并且在读取多播分组数据以便随后读取下一个多播分组的多播分组数据之后，将锁存的开始读取地址重新加载到读取指针。 在一些数据处理实施例中，可以在多处理器系统的两个或多个处理器之间提供多读缓冲器。 在这些实施例中，分组数据的部分可以通过其中一个处理器从缓冲器进行验证和重读。

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