公开(公告)号：US20220344308A1

公开(公告)日：2022-10-27

申请号：US17861580

申请日：2022-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihwan HWANG ,  Taehun KIM ,  Jihwan SUH ,  Soyoun LEE ,  Hyuekjae LEE ,  Jiseok HONG

IPC: H01L25/065 ,  H01L25/00

Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes one or a plurality of chips on a substrate, bumps disposed below each of the one or plurality of chips, an underfill material layer on the substrate, on a side surface of each of the bumps, and extending to side surfaces of the one or plurality of chips, and a mold layer on the substrate and contacting the underfill material layer. The underfill material layer includes a first side portion, a second side portion on the first side portion and having a slope, steeper than a slope of the first side portion, and a third side portion on the second side portion and having a slope that is less steep than a slope of the second side portion.

公开(公告)号：US20220005826A1

公开(公告)日：2022-01-06

申请号：US17148334

申请日：2021-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suhwan LIM ,  Jaehun JUNG ,  Sanghoon KIM ,  Taehun KIM ,  Seongchan LEE

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573

Abstract: A semiconductor device includes gate electrodes and insulating layers spaced apart from each other on a substrate and alternately stacked in a direction perpendicular to an upper surface of the substrate, and channel structures that extend through stack structures. Ones of the structures include a channel insulating layer, a pad layer on the channel insulating layer, and a channel layer. The channel layer includes a first channel region, and a second channel region including a semiconductor material having a length shorter than a length of the first channel region and having an impurity concentration of a first conductivity type and the pad layer includes a semiconductor material doped with a second conductivity type impurity. A height level of a lower surface of the second channel region is lower than a height level of a lower surface of a first erase gate electrode.

公开(公告)号：US20250126792A1

公开(公告)日：2025-04-17

申请号：US18990188

申请日：2024-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suhwan LIM ,  Nambin KIM ,  Samki KIM ,  Taehun KIM ,  Hanvit YANG ,  Changhee LEE ,  Jaehun JUNG ,  Hyeongwon CHOI

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a lower structure including a semiconductor substrate and circuit devices on the semiconductor substrate; a stack structure including interlayer insulating layers and gate electrodes alternating in a vertical direction; and a channel structure penetrating the stack structure. The channel structure includes a core insulating layer, a channel layer, a gate dielectric layer, and a channel pad. A portion of the channel pad overlaps an uppermost gate electrode among the gate electrodes in a horizontal direction. The channel pad includes a first pad layer and a second pad layer on the first pad layer. The second pad layer includes doped polysilicon that is doped with impurities and having N-type conductivity. The first pad layer includes at least one of an undoped polysilicon region and a doped polysilicon region having N-type conductivity and having an impurity concentration lower than an impurity concentration of the second pad layer.

公开(公告)号：US20240389322A1

公开(公告)日：2024-11-21

申请号：US18621916

申请日：2024-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Samki KIM ,  Nambin KIM ,  Taehun KIM

IPC: H10B41/35 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A non-volatile memory device may include a substrate having a cell region and a connection region, an electrode structure including electrodes stacked on the substrate and an insulating pattern covering an uppermost electrode among the electrodes, a vertical structure connected with the substrate through the electrode structure in the cell region, a filling insulating layer covering the electrode structure in the connection region, a buffer insulating layer on a cover insulating layer, a conductive pattern, and an upper semiconductor pattern connected with the conductive pattern through the buffer insulating layer. The cover insulating layer may cover the electrode structure, the vertical structure, and the filling insulating layer, and may include a through hole in the cell region and at least one through opening in the connection region. The conductive pattern may have at least a portion in the through hole, and may be connected with the vertical structure.

公开(公告)号：US20240347169A1

公开(公告)日：2024-10-17

申请号：US18594639

申请日：2024-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung KIM ,  Wooil KIM ,  Taehun KIM ,  Donghyun ROH ,  Jinwoo SONG ,  Jaehun LEE ,  Jungbae YI ,  Hwangrae LEE ,  Jinmook LIM

IPC: G16H20/60

CPC classification number: G16H20/60

Abstract: An electronic apparatus and a controlling method thereof are provided. The electronic apparatus includes memory storing one or more computer programs, and one or more processors communicatively coupled to the memory, wherein the one or more computer programs include computer-executable instructions executed by the one or more processors and wherein the one or more processors configured to acquire nutritional ingredient information corresponding to food information in case of acquiring the food information, acquire candidate food probability information based on the nutritional ingredient information, and acquire final food group capacity information corresponding to the food information based on the nutritional ingredient information and the candidate food probability information.

公开(公告)号：US20240266474A1

公开(公告)日：2024-08-08

申请号：US18430747

申请日：2024-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehun KIM ,  Gyeongseon PARK ,  Hanul YOO ,  Suyeol LEE ,  Taesung JANG ,  Dooho JEONG

IPC: H01L33/40 ,  H01L33/32

CPC classification number: H01L33/405 ,  H01L33/32

Abstract: A semiconductor light emitting device includes a first conductivity type semiconductor layer, a second conductivity type semiconductor layer arranged on the first conductivity type semiconductor layer, an active layer, an electrode layer formed on a top surface of the second conductivity type semiconductor layer, a reflective layer formed on a part of a top surface of the electrode layer, a bonding pad formed on a top surface of the reflective layer, an insulating layer formed on another part of the top surface of the electrode layer, and an insulating spacer conformally formed along a surface of the substrate. The reflective layer includes a material that is not etched by an aqueous solution including one of tetramethyl ammonium hydroxide (TMAH), KOH, NaOH, and NH4OH and the bonding pad has a shell shape including a part of which the width gradually decreases as the part distances from the reflective layer.

公开(公告)号：US20240121958A1

公开(公告)日：2024-04-11

申请号：US18243200

申请日：2023-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Samki KIM ,  Nambin KIM ,  Taehun KIM ,  Suhwan LIM ,  Hyeongwon CHOI

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: A vertical semiconductor device includes; a pattern structure including a plurality of insulation patterns and a plurality of gate electrodes that are alternately and repeatedly stacked on a substrate, wherein the pattern structure includes a first gate electrode serving as a gate electrode of an erase transistor, wherein the first gate electrode is one of the plurality of gate electrodes; and a channel structure in a channel hole passing through the pattern structure, wherein the channel structure includes a data storage structure, a first channel, an undoped semiconductor liner, a doped semiconductor pattern, a filling insulation pattern and a capping pattern, wherein the data storage structure, the first channel, the undoped semiconductor liner, and the doped semiconductor pattern are sequentially disposed on a sidewall of the first gate electrode.

公开(公告)号：US20240003484A1

公开(公告)日：2024-01-04

申请号：US18368663

申请日：2023-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehun KIM ,  Chulyong CHO ,  Jisu KIM ,  Hyunyong CHOI

IPC: F16M11/10 ,  H05K5/00 ,  H05K5/02 ,  F16M11/04 ,  F16M11/18 ,  F16M11/20 ,  F16M11/14 ,  F16M13/02

CPC classification number: F16M11/105 ,  H05K5/0017 ,  H05K5/0217 ,  F16M11/041 ,  F16M11/18 ,  F16M11/2014 ,  F16M11/14 ,  F16M13/022

Abstract: A display apparatus includes a display module, a supporting device provided to support and turn the display module, and a holding device provided for a mobile device to be coupled to the display module. The supporting device rotatably supports the display module and includes a motor providing a driving force to turn the display module. The holding device supports a mobile device so that the mobile device may be coupled to the display module. The holding device comprises a mounting part provided to be mounted onto the display module and a holder rotatably coupled to the mounting part and provided to support the mobile device.

公开(公告)号：US20230035421A1

公开(公告)日：2023-02-02

申请号：US17720376

申请日：2022-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suhwan LIM ,  Nambin KIM ,  Samki KIM ,  Taehun KIM ,  Hanvit YANG ,  Changhee LEE ,  Jaehun JUNG ,  Hyeongwon CHOI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11526

Abstract: A semiconductor device includes a lower structure including a semiconductor substrate and circuit devices on the semiconductor substrate; a stack structure including interlayer insulating layers and gate electrodes alternating in a vertical direction; and a channel structure penetrating the stack structure. The channel structure includes a core insulating layer, a channel layer, a gate dielectric layer, and a channel pad. A portion of the channel pad overlaps an uppermost gate electrode among the gate electrodes in a horizontal direction. The channel pad includes a first pad layer and a second pad layer on the first pad layer. The second pad layer includes doped polysilicon that is doped with impurities and having N-type conductivity. The first pad layer includes at least one of an undoped polysilicon region and a doped polysilicon region having N-type conductivity and having an impurity concentration lower than an impurity concentration of the second pad layer.

公开(公告)号：US20220130801A1

公开(公告)日：2022-04-28

申请号：US17568558

申请日：2022-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuekjae LEE ,  Jihoon KIM ,  Jihwan SUH ,  Soyoun LEE ,  Jiseok HONG ,  Taehun KIM ,  Jihwan HWANG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/16

Abstract: Provided is a semiconductor package including a semiconductor stack including a first lower chip, a second lower chip, a gap filler disposed between the first lower chip and the second lower chip, and a first upper chip disposed on an upper surface of the first lower chip, an upper surface of the second lower chip, and an upper surface of the gap filler, the first lower chip includes first upper surface pads and a first upper surface dielectric layer, the second lower chip includes second upper surface pads and a second upper surface dielectric layer, the first upper chip includes lower surface pads and a lower surface dielectric layer, and an area of an upper surface of each of the second upper surface pads is greater than an area of a lower surface of each of the lower surface pads.