公开(公告)号：US20220399228A1

公开(公告)日：2022-12-15

申请号：US17545468

申请日：2021-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Minsu SEOL ,  Sangwon KIM ,  Kyung-Eun BYUN ,  Hyeonjin SHIN

IPC: H01L21/768 ,  H01L23/532

Abstract: Disclosed are an interconnect structure, an electronic device including the same, and a method of manufacturing the interconnect structure. The interconnect structure includes a dielectric layer; a conductive interconnect on the dielectric layer; and a graphene cap layer on the conductive interconnect. The graphene cap layer contains graphene quantum dots, has a carbon content of 80 at % or more, and has an oxygen content of 15 at % or less.

公开(公告)号：US20210226010A1

公开(公告)日：2021-07-22

申请号：US17111965

申请日：2020-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Minsu SEOL ,  Hyeonjin SHIN

IPC: H01L29/10 ,  H01L29/36 ,  H01L29/423

Abstract: A transistor including at least one two-dimensional (2D) channel is disclosed. A transistor according to some example embodiments includes first to third electrodes separated from each other, and a channel layer that is in contact with the first and second electrodes, parallel to the third electrode, and includes at least one 2D channel. The at least one 2D channel includes at least two regions having different doping concentrations. A transistor according to some example embodiments includes: first to third electrodes separated from each other; a 2D channel layer that is in contact with the first and second electrodes and parallel to the third electrode; a first doping layer disposed under the 2D channel layer corresponding to the first electrode; and a second doping layer disposed under the 2D channel layer corresponding to the second electrode, wherein the first and second doping layers contact the 2D channel layer.

公开(公告)号：US20190016906A1

公开(公告)日：2019-01-17

申请号：US15944920

申请日：2018-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Sangwon KIM ,  Hyeonjin SHIN ,  Dongwook LEE ,  Seongjun PARK ,  Yunseong LEE ,  Seongjun JEONG ,  Alum JUNG

IPC: C09D7/63 ,  C07F3/02 ,  G03F7/16 ,  G03F7/20 ,  G03F7/38 ,  G03F7/32 ,  H01L21/311 ,  H01L21/3213

Abstract: Provided are a hardmask composition including a structure represented by Formula 1 and a solvent, a method of forming a pattern using the hardmask composition, and a hardmask formed from the hardmask composition. wherein in Formula 1, R1 to R8, X, and M are described in detail in the detailed description.

公开(公告)号：US20170025273A1

公开(公告)日：2017-01-26

申请号：US14984189

申请日：2015-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Minsu SEOL ,  Hyeonjin SHIN ,  Sangwon KIM ,  Seongjun PARK

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3215 ,  H01L21/02

CPC classification number: H01L21/0332 ,  H01L21/02118 ,  H01L21/02274

Abstract: A 2D material hard mask includes hydrogen, oxygen, and a 2D material layer having a layered crystalline structure. The 2D material layer may be a material layer including one of a carbon structure (for example, a graphene sheet) and a non-carbon structure.

Abstract translation: 2D材料硬掩模包括氢，氧和具有层状晶体结构的2D材料层。 2D材料层可以是包括碳结构（例如，石墨烯片）和非碳结构之一的材料层。

公开(公告)号：US20250107191A1

公开(公告)日：2025-03-27

申请号：US18897189

申请日：2024-09-26

Applicant: Samsung Electronics Co., Ltd. ,  KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Minseok YOO ,  Kibum KANG ,  Minseung GYEON ,  Minsu SEOL

IPC: H01L29/24 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device may include a channel layer including a channel region, a source region, and a drain region, the source region and the drain region being on both sides of the channel region, respectively; a source electrode connected to the source region, a drain electrode connected to the drain region, and a gate electrode on the channel region. The channel region may include a first two-dimensional material layer including a noble metal-based two-dimensional semiconductor material and a second two-dimensional material layer including a two-dimensional semiconductor material different from the first two-dimensional material layer.

公开(公告)号：US20240186183A1

公开(公告)日：2024-06-06

申请号：US18441520

申请日：2024-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Minhyun LEE ,  Junyoung KWON ,  Hyeonjin SHIN ,  Minseok YOO

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/06 ,  H01L29/16 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/76 ,  H01L29/786

CPC classification number: H01L21/823412 ,  H01L21/02521 ,  H01L21/02527 ,  H01L21/02568 ,  H01L21/0259 ,  H01L21/823431 ,  H01L29/0665 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66045 ,  H01L29/66969 ,  H01L29/7606 ,  H01L29/78696

Abstract: Disclosed are a field effect transistor and a method of manufacturing the same. The field effect transistor includes a source electrode on a substrate, a drain electrode separated from the source electrode, and channels connected between the source electrode and the drain electrode, gate insulating layers, and a gate electrode. The channels may have a hollow closed cross-sectional structure when viewed in a first cross-section formed by a plane across the source electrode and the drain electrode in a direction perpendicular to the substrate. The gate insulating layers may be in the channels. The gate electrode may be insulated from the source electrode and the drain electrode by the gate insulating layers.

公开(公告)号：US20240178294A1

公开(公告)日：2024-05-30

申请号：US18347929

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunkyu LEE ,  Keunwook SHIN ,  Minsu SEOL

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/18 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/18 ,  H01L29/41733 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include a first electrode and a second electrode on a substrate and arranged perpendicular to a surface of the substrate, a plurality of channel layers between the first electrode and the second electrode, and a gate electrode surrounding the plurality of channel layers. The plurality of channel layers may be inclined with respect to a direction from the first electrode to the second electrode. An electronic device may include the semiconductor device.

公开(公告)号：US20240164115A1

公开(公告)日：2024-05-16

申请号：US18504760

申请日：2023-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Minsu SEOL ,  Yunseong LEE ,  Dongmin KIM ,  Sanghyun JO ,  Dukhyun CHOE

IPC: H10B53/30 ,  H01L21/28 ,  H01L29/04 ,  H01L29/51

CPC classification number: H10B53/30 ,  H01L29/045 ,  H01L29/40111 ,  H01L29/516

Abstract: Provided are a semiconductor device including a ferroelectric and an electronic apparatus including the semiconductor device. The semiconductor device includes a semiconductor layer, an electrode apart from the semiconductor layer, and a ferroelectric layer arranged between the semiconductor layer and the electrode. The ferroelectric layer includes a plurality of crystal grains, each of which having a first crystal orientation aligned within an angle range with respect to a first direction and having a second crystal orientation aligned within an angle range with respect to a second direction that is different from the first direction.

公开(公告)号：US20240038845A1

公开(公告)日：2024-02-01

申请号：US18335487

申请日：2023-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minseok YOO ,  Minsu SEOL ,  Junyoung KWON ,  Kyung-Eun BYUN

IPC: H01L29/10 ,  H01L29/778 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/1033 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/66795 ,  H01L29/66431 ,  H01L29/41791

Abstract: A layer structure including a two-dimensional (2D) channel layer, a method of manufacturing a two-dimensional (2D) channel layer, an electronic device including the layer structure, and an electronic apparatus including the layer structure are disclosed. The layer structure may include a first substrate, a second substrate surrounded by the first substrate, and a 2D channel layer on the second substrate. An interfacial energy of the second substrate may be less than an interfacial energy of the first substrate. The method of manufacturing a 2D channel layer may include forming a second substrate to be surrounded by a first substrate, forming a precursor layer for forming a 2D channel on any one of the first and second substrates, and transforming the precursor layer into a liquid precursor layer. The interfacial energy of the second substrate may be less than the interfacial energy of the first substrate.

公开(公告)号：US20230077783A1

公开(公告)日：2023-03-16

申请号：US18056446

申请日：2022-11-17

Applicant: Samsung Electronics Co.,Ltd

Inventor： Minhyun LEE ,  Minsu SEOL ,  Yeonchoo CHO ,  Hyeonjin SHIN

IPC: H01L29/10 ,  H01L29/24 ,  H01L29/423

Abstract: A field effect transistor includes a substrate, a source electrode and a drain electrode on the substrate and apart from each other in a first direction, a plurality of channel layers, a gate insulating film surrounding each of the plurality of channel layers, and a gate electrode surrounding the gate insulating film. Each of the plurality of channel layers has ends contacting the source electrode and the drain electrode. The plurality of channel layers are spaced apart from each other in a second direction away from the substrate. The plurality of channel layers include a 2D semiconductor material.