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    ELECTRICALLY CONDUCTIVE THIN FILMS
    21.
    发明申请
    ELECTRICALLY CONDUCTIVE THIN FILMS 有权
    电导电薄膜

    公开(公告)号：US20160141067A1

    公开(公告)日：2016-05-19

    申请号：US14940223

    申请日：2015-11-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kimoon LEE ,  Sang Il KIM ,  Se Yun KIM ,  Sung Woo HWANG ,  Woojin LEE ,  Hee Jung PARK ,  Yoon Chul SON ,  Hyosug LEE ,  Doh Won JUNG ,  Youngjin CHO ,  Jae-Young CHOI

    IPC: H01B1/06

    CPC classification number: H01B1/02 ,  C01B19/002 ,  C01B19/007 ,  C01P2002/20 ,  C01P2002/30 ,  C01P2002/90 ,  C30B7/00 ,  C30B29/46 ,  C30B29/60 ,  C30B29/605 ,  C30B29/607 ,  H01B1/06 ,  H01L21/02417 ,  H01L21/02573 ,  H01L21/02609

    Abstract: An electrically conductive thin film including: a material including a compound represented by Chemical Formula 1 and having a layered crystal structure, MemAa   Chemical Formula 1 wherein Me is Al, Ga, In, Si, Ge, Sn, A is S, Se, Te, or a combination thereof, and m and a each are independently a number selected so that the compound of Chemical Formula 1 is neutral; and a dopant disposed in the compound of Chemical Formula 1, wherein the dopant is a metal dopant that is different from Me and has an oxidation state which is greater than an oxidation state of Me, a non-metal dopant having a greater number of valence electrons than a number of valence electrons of A in Chemical Formula 1, or a combination thereof, and wherein the compound of Chemical Formula 1 includes a chemical bond which includes a valence electron of an s orbital of Me.

    Abstract translation: 一种导电薄膜，包括：包含由化学式1表示并具有层状晶体结构的化合物的材料，其中Me为Al，Ga，In，Si，Ge，Sn，A的MemAa化学式1为S，Se，Te ，或它们的组合，m和a各自独立地选择为使化学式1的化合物为中性的数字; 以及配置在化学式1的化合物中的掺杂剂，其中所述掺杂剂是与Me不同的金属掺杂剂，并且具有大于Me的氧化态的氧化态，具有更大数量化合价的非金属掺杂剂 电子与化学式1中A的多价价电子或其组合，其中化学式1的化合物包括包含Me轨道的价电子的化学键。

    INTEGRATED CIRCUIT DEVICE
    22.
    发明公开
    INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20240234250A9

    公开(公告)日：2024-07-11

    申请号：US18320423

    申请日：2023-05-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sangkoo KANG ,  Wookyung YOU ,  Minjae KANG ,  Koungmin RYU ,  Hoonseok SEO ,  Woojin LEE ,  Junchae LEE

    IPC: H01L23/48 ,  H01L21/762 ,  H01L21/768 ,  H01L27/088

    CPC classification number: H01L23/481 ,  H01L21/76224 ,  H01L21/76898 ,  H01L27/088 ,  H01L29/66439

    Abstract: An integrated circuit (IC) device includes a substrate, a pair of fin-type active regions protruding from the substrate to define a trench region on the substrate, the fin-type active regions extending in a first lateral direction, a pair of source/drain regions on the fin-type active regions, respectively, a device isolation film in the trench region, the device isolation film apart from the substrate in a vertical direction, an etch stop structure filling at least a portion of the trench region between the substrate and the device isolation film, a via power rail between the pair of fin-type active regions and between the pair of source/drain regions, the via power rail passing through at least a portion of the etch stop structure, and a backside power rail passing through the substrate, the backside power rail in contact with one end of the via power rail.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    24.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20230114920A1

    公开(公告)日：2023-04-13

    申请号：US18079998

    申请日：2022-12-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Woojin LEE ,  Hoon Seok SEO ,  Sanghoon AHN ,  Kyu-Hee HAN

    IPC: H01L21/768 ,  H01L23/528

    Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

    INTEGRATED CIRCUIT DEVICE INCLUDING AIR GAPS AND METHOD OF MANUFACTURING THE SAME
    25.
    发明申请
    INTEGRATED CIRCUIT DEVICE INCLUDING AIR GAPS AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20230072375A1

    公开(公告)日：2023-03-09

    申请号：US17984874

    申请日：2022-11-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sanghoon AHN ,  Woojin LEE ,  Kyuhee HAN

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: An integrated circuit device according to the inventive concepts includes lower wiring structures formed on a substrate, an air gap arranged between the lower wiring structures, a capping layer covering an upper surface of the air gap, an etch stop layer conformally covering an upper surfaces of the lower wiring structures and the capping layer and having a protrusion and recess structure, an insulating layer covering the etch stop layer, and an upper wiring structure penetrating the insulating layer and connected to the upper surface of the lower wiring structure not covered with the etch stop layer, wherein the upper wiring structure covers a portion of an upper surface of the capping layer, and a level of the upper surface of the capping layer is higher than a level of the upper surface of the lower wiring structures.

    SEMICONDUCTOR DEVICE
    26.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210166974A1

    公开(公告)日：2021-06-03

    申请号：US17174409

    申请日：2021-02-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Woojin LEE ,  Hoon Seok SEO ,  Sanghoon AHN ,  Kyu-Hee HAN

    IPC: H01L21/768 ,  H01L23/528

    Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
    27.
    发明申请
    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20210005548A1

    公开(公告)日：2021-01-07

    申请号：US16742233

    申请日：2020-01-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Woojin LEE ,  Junghoo SHIN ,  Sanghoon AHN ,  Junhyuk LIM ,  Daehan KIM

    IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

    Abstract: An integrated circuit device includes a first insulation layer on a substrate, a lower wiring structure in the first insulation layer and including a metal layer and a conductive barrier layer, such that the metal layer is on the conductive barrier layer, an etch stop layer overlapping an upper surface of the first insulation layer and an upper surface of the conductive barrier layer and having a first thickness, a capping layer overlapping a portion of the upper surface of the metal layer and having a second thickness which is less than the first thickness, a second insulation layer overlapping the etch stop layer and the capping layer, and an upper wiring structure connected to another portion of the upper surface of the metal layer not overlapped by the capping layer in the second insulation layer.

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