公开(公告)号：US20220286139A1

公开(公告)日：2022-09-08

申请号：US17573555

申请日：2022-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwook Park ,  Changkyoun Oh

IPC: H03M1/10

Abstract: In a method of operating an analog-to-digital converter, a gain error and an offset error that are associated with a digital code generated from the analog-to-digital converter are obtained by performing a first analog-to-digital conversion on a first input analog signal. The gain error and the offset error are stored. A calibration digital code is generated by performing a second analog-to-digital conversion on a second input analog signal based on the gain error and the offset error.

公开(公告)号：US11411068B2

公开(公告)日：2022-08-09

申请号：US17126939

申请日：2020-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwook Park

IPC: H01L23/522 ,  H01L23/00 ,  H01L49/02 ,  H01F5/00 ,  H01L23/538

Abstract: A semiconductor package may include a substrate, including an inductor array including inductor structures, and a semiconductor chip and a voltage regulator each on the substrate. Each of the inductor structures may include an input terminal, an output terminal, a coil between the input terminal and the output terminal, and conductive wirings. The inductor structures may be apart from one another in a second horizontal direction. Each of the coils may include a lower horizontal winding wound horizontally, an upper horizontal winding wound horizontally, and a conductive via. In a plan view, the coils may be arranged in zigzags, and the coils and the conductive wirings may be alternately arranged in the second horizontal direction.

公开(公告)号：US09275903B2

公开(公告)日：2016-03-01

申请号：US14488883

申请日：2014-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Soo Kwak ,  Youngsu Kim ,  Sangwook Park ,  Taeje Cho

IPC: H01L21/78 ,  H01L21/02 ,  H01L21/268 ,  H01L21/683 ,  H01L23/544

CPC classification number: H01L21/78 ,  H01L21/02013 ,  H01L21/268 ,  H01L21/6835 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device include preparing an initial substrate including an edge region and a central region in which circuit patterns are formed, forming a reforming region in the edge region of the initial substrate, grinding the initial substrate to form a substrate, and cutting the substrate to form a semiconductor chip including each of the circuit patterns. A crystal structure of the reforming region is different from that of the initial substrate.

Abstract translation: 制造半导体器件的方法包括制备包括边缘区域和形成电路图案的中心区域的初始衬底，在初始衬底的边缘区域中形成重整区域，研磨初始衬底以形成衬底，以及 切割基板以形成包括每个电路图案的半导体芯片。 重整区域的晶体结构与初始衬底的晶体结构不同。

公开(公告)号：US20130267066A1

公开(公告)日：2013-10-10

申请号：US13909628

申请日：2013-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangwook Park ,  Jonggi Lee ,  Wonchul Lim

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/20 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83143 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2924/00

Abstract: Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a semiconductor chip having a bonding pad, a metal line electrically connected to the semiconductor chip and having a terminal contacting an external terminal, an insulation layer covering the metal line and having an opening that defines the terminal, and a molding layer molding the semiconductor chip, wherein the molding layer includes a recess pattern exposing the bonding pad and extending from the bonding pad to the terminal, and the metal line is embedded in the recess pattern to contact the bonding pad.

Abstract translation: 提供半导体封装及其制造方法。 半导体封装包括具有接合焊盘的半导体芯片，与半导体芯片电连接并具有与外部端子接触的端子的金属线，覆盖金属线并具有限定端子的开口的绝缘层，以及模制层 模制所述半导体芯片，其中所述模制层包括暴露所述焊盘并从所述焊盘延伸到所述端子的凹陷图案，并且所述金属线嵌入所述凹槽图案中以接触所述焊盘。

公开(公告)号：US12159111B2

公开(公告)日：2024-12-03

申请号：US17536907

申请日：2021-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonho Lee ,  Munjo Kim ,  Sangwook Park ,  Youngbin Shin ,  Kookjin Yeo

IPC: G06F40/30 ,  G06F40/103 ,  G06F40/166 ,  G06F40/279 ,  G06N20/00 ,  G10L15/18 ,  G10L15/22 ,  G10L15/30 ,  G10L15/08

Abstract: A system and method for providing a voice assistant service for text including an anaphor are provided. A method, performed by an electronic device, of providing a voice assistant service includes: obtaining first text generated from a first input, detecting a target word within the first text and generating common information related to the detected target word, using a first natural language understanding (NLU) model, obtaining second text generated from a second input, inputting the common information and the second text to a second NLU model, detecting an anaphor included in the second text and outputting an intent and a parameter, based on common information corresponding to the detected anaphor, using the second NLU model, and generating response information related to the intent and the parameter.

公开(公告)号：US12106795B2

公开(公告)日：2024-10-01

申请号：US17724006

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeongsik Ryu ,  Bokyeon Won ,  Kyoungmin Kim ,  Donggeon Kim ,  Sangwook Park ,  Inseok Baek

IPC: G11C11/408

CPC classification number: G11C11/4085

Abstract: A memory device includes a first sub wordline driver including a first active region connected to a first wordline through a first direct contact, and a first transistor connected to a first gate line, the first gate line and the first wordline extending in a first direction, and a second sub wordline driver including a second active region connected to a second wordline through a second direct, the second direct contact and first direct contact extending in parallel in a second direction, the second direction being perpendicular to the first direction. A second transistor is connected to a second gate line. The second gate line extends in the first direction. A third wordline driven by a third sub wordline driver is between the first wordline and the second wordline.

公开(公告)号：US12056517B2

公开(公告)日：2024-08-06

申请号：US17674540

申请日：2022-02-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonho Lee ,  Sangwook Park ,  Youngbin Shin ,  Kookjin Yeo

IPC: G06F3/048 ,  G06F9/48 ,  G10L15/26

CPC classification number: G06F9/4843 ,  G10L15/26

Abstract: Disclosed are an electronic device and a method for controlling thereof. According to an embodiment, a method for controlling an electronic apparatus includes: obtaining a voice command while a first application is executed in foreground; obtaining a text by recognizing the voice command; identifying at least one second application to perform the voice command based on the text; based on information of the first application and the at least one second application; identify whether to execute each of the first application and the at least one second application in the foreground or background of the electronic apparatus; and providing the first application and the at least one second application based on the identification.

公开(公告)号：US11735248B2

公开(公告)日：2023-08-22

申请号：US17685849

申请日：2022-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokjae Lee ,  Bok-Yeon Won ,  Kyoungmin Kim ,  Donggeon Kim ,  Myeongsik Ryu ,  Sangwook Park ,  Inseok Baek

IPC: G11C11/408 ,  H10B12/00

CPC classification number: G11C11/4085 ,  H10B12/50 ,  H10B12/315 ,  H10B12/34

Abstract: A sub-word-line driver and semiconductor memory devices including the same are provided. The sub-word-line driver may include a word line pull-up transistor, a word line pull-down transistor, and a keeping transistor configured to maintain a word line at a specified voltage level. The sub-word-line driver may include a peripheral active region on a substrate, a first peripheral gate electrode that corresponds to a gate node of the word line pull-down transistor on the peripheral active region, a second peripheral gate electrode that corresponds to a gate node of the keeping transistor on the peripheral active region, and a first lower contact coupled to a first region of the peripheral active region. A first (VBB) voltage from the first region may be supplied to a source node of the keeping transistor.

公开(公告)号：US11699227B2

公开(公告)日：2023-07-11

申请号：US17384366

申请日：2021-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heungsuk Oh ,  Mincheol Kang ,  Sangwook Park

IPC: G06K9/00 ,  G06T7/00 ,  G06T7/50 ,  G06T7/60 ,  G03F1/36 ,  G06V10/30 ,  G06V10/42 ,  G06V10/88 ,  G06F18/22 ,  G06F18/214

CPC classification number: G06T7/0006 ,  G03F1/36 ,  G06F18/2148 ,  G06F18/22 ,  G06T7/50 ,  G06T7/60 ,  G06V10/30 ,  G06V10/42 ,  G06V10/88 ,  G06T2207/10061 ,  G06T2207/20081 ,  G06T2207/20084 ,  G06T2207/30148

Abstract: A method of fabricating a semiconductor device includes generating a mask based on second layout data obtained by applying an OPC model to first layout data and performing a semiconductor process using the mask on a substrate, obtaining a plurality of pattern images by selecting a plurality of sample patterns from the substrate, selecting sample images corresponding to the sample patterns from each of the first layout data, the second layout data, and simulation data obtained by performing a simulation based on the second layout data, generating a plurality of input images corresponding to the sample patterns by blending the sample images corresponding to the sample patterns, respectively, and generating an error prediction model for the OPC model by training a machine learning model using a data set including the input images and the pattern images.

公开(公告)号：US20220406360A1

公开(公告)日：2022-12-22

申请号：US17685849

申请日：2022-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokjae Lee ,  Bok-Yeon Won ,  Kyoungmin Kim ,  Donggeon Kim ,  Myeongsik Ryu ,  Sangwook Park ,  Inseok Baek

IPC: G11C11/408 ,  H01L27/108

Abstract: A sub-word-line driver and semiconductor memory devices including the same are provided. The sub-word-line driver may include a word line pull-up transistor, a word line pull-down transistor, and a keeping transistor configured to maintain a word line at a specified voltage level. The sub-word-line driver may include a peripheral active region on a substrate, a first peripheral gate electrode that corresponds to a gate node of the word line pull-down transistor on the peripheral active region, a second peripheral gate electrode that corresponds to a gate node of the keeping transistor on the peripheral active region, and a first lower contact coupled to a first region of the peripheral active region. A first (VBB) voltage from the first region may be supplied to a source node of the keeping transistor.